Applications Engineering, Engineer
Originally posted 1 October 2026 by the employer.
This role focuses on supporting design teams using ICV and StarRC.
About the role
This role provides technical support and methodology development for design teams utilizing Synopsys's ICV and StarRC tools. You will help design teams address complex extraction and physical signoff challenges using ICV and StarRC.
What you'll do
- Provide direct technical support to design teams using ICV and StarRC for signoff readiness and successful tape-outs.
- Debug complex ICV physical verification and StarRC parasitic extraction issues, including design rule violations, layout-versus-schematic discrepancies, RC modeling anomalies, and timing correlation problems across advanced process nodes.
- Develop and refine ICV and StarRC signoff methodologies that improve verification and extraction accuracy, reduce runtime, and support reliable full-chip analysis at scale.
- Collaborate with customer engineering teams and senior colleagues during critical tape-out phases to analyze blocking ICV and StarRC issues.
- Assist with technical guidance and training for customer teams on ICV and StarRC workflows, physical verification, RC modeling techniques, and signoff best practices.
- Work directly with Synopsys R&D teams to communicate customer requirements, reproduce ICV and StarRC issues, and validate fixes and enhancements.
What you'll need
- Entry-level to approximately 2 years of relevant experience in applications engineering, semiconductor design, physical verification, or parasitic extraction.
- Foundational knowledge of physical verification and parasitic extraction, with experience using EDA tools.
- Basic understanding of semiconductor design, foundry flows, design rule checking, layout-versus-schematic verification, and RC extraction concepts.
- Working knowledge of Linux/Unix environments and scripting languages such as Tcl or Python.
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
Nice to have
- Hands-on exposure to ICV and/or StarRC.
- Strong Korean and English communication skills.
Skills: ICV, StarRC, physical verification, parasitic extraction, signoff
This role has been open 0 days — well below the 30-day median for Applications FAE roles.
Applications FAE · EDA Tools
|
Open roles in category
97
|
Median days open
30 d
|
Median salary
$163k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (97 roles · 11 employers) |
|---|---|---|
| Open roles in this specialty | 46 | 97 |
| Median days open | 16 d | 30 d (−14 d vs this employer) |
| Median salary (USD postings) | — | $163k |
Skills observed across this category: ICV, StarRC, physical verification, parasitic extraction, signoff
Who's hiring in this category
- Synopsys (this employer) · 44 open roles · median 16 d
- Cadence Design Systems · 20 open roles · median 57 d
- Renesas Electronics · 14 open roles · median 49 d
- Keysight Technologies · 6 open roles · median 79 d
- GlobalFoundries · 4 open roles · median 63 d
- AMD · 2 open roles · median 74 d
How we counted: 97 open Applications FAE (EDA Tools) roles from 11 employers tracked in the SemiconductorJobs index, counted 2 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.