Applications Engineer - Silicon IP

Originally posted 27 August 2026 by the employer.

About the role

This role involves helping customers evaluate, integrate, verify, and physically implement silicon IP in their SoCs. The focus is on facilitating silicon IP integration, verifying environments, closing coverage and timing, and resolving integration issues for the Electron E1 processor.

What you'll do

• Serve as the primary technical point of contact for customers integrating silicon IP, from RTL simulation and UVM testbench setup through synthesis, floorplanning, place-and-route, timing closure, and signoff.
• Debug customer-reported issues across RTL, testbench, constraints, and physical implementation boundary, distinguishing IP defects from configuration errors or protocol misunderstandings.
• Develop and maintain reference verification environments, example testbenches, implementation flows, floorplan guidance, and integration collateral, including SDC and UPF templates.
• Deliver onsite and remote technical training on IP architecture, verification methodology, verification IP usage, coverage closure, timing models, physical abstracts, and implementation best practices.
• Support pre-sales technical evaluations by helping prospective customers assess IP quality, verification collateral, PPA, floorplan compatibility, node/process readiness, and integration effort.
• Advise customers on interface and protocol integration, multi-voltage and power-domain design, DFT stitching at the IP boundary, and node-specific signoff requirements.

What you'll need

• BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 5+ years of experience in ASIC/SoC verification, physical design, silicon IP integration, or a closely related applications engineering role.
• Strong scripting and automation skills (Python, TCL, Make, or shell) for building flows, regressions, and debug tooling.
• Hands-on experience integrating third-party or internally licensed silicon IP, such as soft or hard macros, protocol or interface IP, interconnect, standard-cell libraries, or memory compilers.
• Experience diagnosing complex integration issues and translating deep technical findings into clear, actionable guidance.
• Familiarity with multiple foundries or process nodes and the verification, PPA, reliability, and signoff challenges associated with them.
• Strong SystemVerilog/UVM skills, comfort reading and debugging RTL, and experience with coverage-driven verification using simulators such as Xcelium, VCS, or Questa, OR practical experience with synthesis, floorplanning, place-and-route, and static timing analysis using tools such as Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime, or Tempus, OR working knowledge of timing models and physical abstracts (Liberty/ECSM/CCS and LEF), constraints and low-power intent (SDC and UPF), and signoff flows (STA, IR/EM, DRC/LVS).

Nice to have

• Experience as an IP vendor applications engineer, verification or physical-design consultant, or silicon IP integrator at a systems/SoC company.
• Experience with formal verification, protocol compliance suites, verification IP, low-power design, SoC-level DFT, or reliability signoff.
• Experience with processor-based SoC integration, cache-coherent fabrics, and high-speed chip-to-chip or peripheral interfaces.

Skills: customer-facing, silicon IP integration, RTL simulation, UVM testbench, physical implementation