Advanced Packaging SI/PI Engineer - San Jose, United States
Originally posted 11 May 2026 by the employer. Relisted by the employer on 27 August 2026.
About the role
As a Signal & Power Integrity Engineer, you will be responsible for the electrical performance of the AI accelerator platform across silicon, package, and board. You will drive power delivery networks and high-speed signaling solutions within 2D/2.5D/3D packages alongside silicon, package, platform, and system teams.
What you'll do
- Execute SI/PI analysis of designs and optimization within 2D/2.5D/3D packages. - Drive SI requirements into interposer/substrate layout (high-speed routing: 112G/224G) from preliminary design through tape-out. - Drive PDN design and decoupling strategy across substrate and interposer, owning DC IR drop, dynamic IR drop, and impedance targets across all rails. - Own ball map / C4 / BGA pin assignment from soft freeze through final freeze in partnership with package layout, ASIC PD, and board layout teams. - Support board-level SI/PI and rack-level scale-up topology studies, including rack test vehicle design and cable characterization. - Collaborate with Package Layout Designers, ASIC PD, IP teams, and Board Schematic/Layout/SI/PI teams to optimize electrical performance.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field with a strong understanding of signal integrity and power integrity concepts and fundamentals. - 8+ years of SI/PI experience on high-performance ASIC, processor, or accelerator platforms. - Proven experience defining and closing PDN for high-power silicon, including substrate and PCB plane design, decap strategy, and dynamic IR/EM analysis. - Experience with developing systems with high-speed interfaces like HBM, SerDes and D2D interfaces. - Hands-on expertise with one or more of: ANSYS HFSS / SIwave, Cadence Sigrity (PowerSI / PowerDC), Keysight ADS. - Experience with CoWoS or equivalent advanced packaging materials and technologies including interposer SI/PI implications, C4 bump planning, and substrate stack-up trade-offs. - Track record of designing and correlating SI/PI test vehicles against silicon measurement during bring-up and lab characterization.
Nice to have
- Familiarity with full RTL-to-GDSII context and how PD decisions interact with package and board PDN. - Experience with multi-die, 2.5D, or 3D packaging signoff, including chip-package-system (CPS) co-design. - Project management experience coordinating across internal teams, OSAT partners, and PCB ODMs. - Familiarity with modern ML and LLM model architectures, accelerator architectures, or HPC system design.
Skills: SI/PI analysis, 2.5D/3D packages, PDN design, HBM, SerDes
This role has been open 165 days — well above the 116-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Chiplet Interconnect
|
Open roles in category
39
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Median days open
116 d
|
Median salary
$219k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Etched | All employers we track in this specialty (39 roles · 18 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 39 |
| Median days open | 165 d | 116 d (+49 d vs this employer) |
| Median salary (USD postings) | — | $219k |
Skills observed across this category: SI/PI analysis, 2.5D/3D packages, PDN design, HBM, SerDes
Who's hiring in this category
- Marvell Technology · 5 open roles · median 52 d
- Qualcomm · 5 open roles · median 116 d
- Intel Corporation · 4 open roles · median 40 d
- Micron Technology · 4 open roles · median 163 d
- NVIDIA · 4 open roles · median 75 d
- GlobalFoundries · 3 open roles · median 43 d
How we counted: 39 open Chiplet/Advanced Packaging Design (Chiplet Interconnect) roles from 18 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.