3rd Party Memory PHY Technical Lead - TX, Austin, United States
Originally posted 16 September 2026 by the employer.
About the role
This role involves serving as the technical owner for third-party Memory/Serdes PHY and mixed-signal IP across all AMD products, from architecture to post-silicon validation and production.
What you'll do
- Serve as the AMD technical owner for selected third-party Memory/Serdes PHY and mixed-signal IP across multiple product programs.
- Provide technical leadership for the IP/PHY throughout the product lifecycle, from architecture to integration to post-silicon validation to production.
- Collaborate directly with third-party IP vendors to support IP evaluation, design transfer, release collateral, and integration into AMD SoCs.
- Partner with SoC integration teams to ensure electrical, logical, and physical quality of IP integration.
- Drive system-level architectural decisions by balancing performance, power, area, cost, and implementation constraints.
- Support package and PCB design teams with signal integrity and power integrity analysis, debug, and optimization.
What you'll need
- Experience designing high-speed mixed-signal IP, with system-level architecture experience.
- Design knowledge of high-speed I/O SerDes or Memory PHY architectures and blocks.
- Experience with one or more interface protocols like HBM, LPDDR, DDR, GDDR, PCIe, Ethernet, USB, DisplayPort, HDMI, MIPI.
- Experience with advanced FinFET semiconductor technologies at and below 7nm.
- Basic understanding of RTL, logic design, and digital circuits.
- B.S. or M.S. Electrical Engineering.
Nice to have
- Python and/or Perl programming.
- Familiarity with UNIX environment.
- Laboratory experience, including hands-on use of equipment: BERT, oscilloscope, logic analyzer.
Skills: Memory/Serdes PHY, high-speed mixed-signal IP, HBM, LPDDR, DDR, PCIe, Ethernet, signal integrity
This role has been open 27 days — well below the 81-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
241
|
Median days open
81 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (241 roles · 48 employers) |
|---|---|---|
| Open roles in this specialty | 30 | 241 |
| Open roles in the wider Analog & Mixed-Signal family | 38 | 1399 · 105 employers |
| Median days open | 38 d | 81 d (−43 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: Memory/Serdes PHY, high-speed mixed-signal IP, HBM, LPDDR, DDR, PCIe
Who's hiring in this category
- Synopsys · 31 open roles · median 29 d
- AMD (this employer) · 30 open roles · median 38 d
- Cadence Design Systems · 19 open roles · median 187 d
- Qualcomm · 19 open roles · median 61 d
- Micron Technology · 13 open roles · median 74 d
- Apple · 12 open roles · median 15 d
How we counted: 241 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 48 employers tracked in the SemiconductorJobs index, counted 14 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.