3D Stacked DRAM - Logic Verification Engineer
$140,000 - $310,000 USD yearly
Verify digital logic blocks and UVM-based Verification IP for 3D-stacked DRAM and DRAM-on-Logic architectures.
Originally posted 12 November 2026 by the employer.
About the role
This role drives the verification of digital logic blocks and advanced IP for 3D-stacked DRAM, enabling DRAM-on-Logic system configurations with customers. You will verify peripheral logic and DFT features while co-designing logic dies with foundry and customer partners.
What you'll do
- Lead IP verification for 3D-stacked DRAM to enable DRAM-on-Logic configurations.
- Verify digital logic blocks for 3D-stacked DRAM peripherals and DFT features, co-designing logic dies with U.S.-based customers.
- Partner with customers and foundry contacts, including TSMC and Intel, to address 3D-stacked DRAM technical requirements.
- Establish verification environments for service-ready IPs and supporting infrastructure.
- Work with EDA vendors to develop the verification environment and integrate IPs into customer design flows.
What you'll need
- Bachelor’s degree or higher in Electrical Engineering or a related discipline.
- 4+ years of relevant experience in semiconductor design verification, including test planning, verification environment development, simulation, debugging, and coverage analysis.
- Experience performing functional verification of SoCs, in-house and third-party digital IPs, and mixed-signal designs using SystemVerilog and UVM.
- Experience developing specification-driven verification plans, test scenarios, and functional coverage models.
- Hands-on experience in end-to-end development of custom UVM agents and in-house SystemVerilog/UVM-based Verification IP (VIP) for new protocols and custom IP interfaces.
- Experience evaluating, integrating, and utilizing third-party VIP, executing regressions, debugging failures, and driving code and functional coverage closure.
Skills: SystemVerilog, UVM, 3D-stacked DRAM, VIP, functional coverage
More semiconductor jobs: Verification engineer jobs · San Jose jobs
First seen in our index 0 days ago, well below the 62-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1339
|
Median days since first seen
62 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SK Hynix America | All employers we track in this specialty (1339 roles · 99 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 1339 |
| Open roles in the wider Digital Design & Verification family | 2 | 3527 · 120 employers |
| Median days since first seen | 0 d | 62 d (+62 d vs this employer) |
| Median salary (USD postings) | n/a | $185k |
Skills observed across this category: SystemVerilog, UVM, 3D-stacked DRAM, VIP, functional coverage
Who's hiring in this category
- Qualcomm · 120 open roles · median 51 d
- Apple · 108 open roles · median 15 d
- NVIDIA · 108 open roles · median 74 d
- AMD · 79 open roles · median 70 d
- Synopsys · 73 open roles · median 56 d
- SiFive · 57 open roles · median 70 d
How we counted: 1339 open Design Verification (Design Verification) roles from 99 employers tracked in the SemiconductorJobs index, counted 12 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.