3D Stacked DRAM Design Engineer - San Jose, CA, United States
$150,000 - $260,000 USD yearly
Originally posted 16 July 2026 by the employer.
Join a team focused on the co-design of 3D-stacked DRAM logic dies.
About the role
This role involves driving the co-design of 3D-stacked DRAM logic dies to strengthen leadership in the DRAM-on-Logic era. You will collaborate closely with U.S.-based customers to align die design solutions with their evolving technical requirements.
What you'll do
- Strengthen leadership in the DRAM-on-Logic era through optimized DRAM Die design.
- Co-design 3D-stacked DRAM Logic Dies and DRAM-on-Logic solutions with U.S.-based customers.
- Design circuits for 3D-stacked DRAM that meet internal and external specifications, including DRAM DFT implementation.
- Review specifications and define the architecture for 3D-stacked DRAM products.
- Improve design quality and yield throughout the 3D-stacked DRAM development phase.
- Enhance performance and ensure stable operation to meet customer requirements during product development.
What you'll need
- Bachelor’s degree or higher in Electrical Engineering or a related discipline with 4+ years of relevant experience.
- Development of DRAM and design DRAM circuit based on custom design methodology (using virtuoso [or similar tools], spice simulator).
- Experience reviewing DRAM specifications and architecture.
- Circuit design experience to meet internal and external requirements for DRAM products.
- Experience evaluating compliance with DRAM specifications through design analysis at the wafer levels test / package levels test / system level test.
- Experience in full custom + digital Co-design and PDN analysis.
- Experience in full custom-based logic foundry design.
- Expert in Python, and circuit simulators (HSPICE, PrimeSim, Spectre, etc.).
Skills: 3D-stacked DRAM, DRAM peripheral circuits, DRAM DFT, custom design methodology, circuit design
This role has been open 80 days — well above the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SK Hynix America | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 287 |
| Median days open | 68 d | 69 d (−1 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: 3D-stacked DRAM, DRAM peripheral circuits, DRAM DFT, custom design methodology, circuit design
Who's hiring in this category
- Micron Technology · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.