2027 PhD SerDes Optical Transceivers Silicon Design and Architecture Modeling Engineer Intern/Co-op
Originally posted 11 September 2026 by the employer.
This internship/co-op focuses on advanced optical transceiver and SerDes technologies.
About the role
This role involves working on advanced optical transceiver and SerDes technologies, with a focus on silicon design and architecture modeling projects related to SerDes optical transceivers.
What you'll do
- Work alongside experienced engineers on advanced optical transceiver and SerDes technologies.
- Understand technical problem statements, define objectives, and explore potential solutions.
- Research, evaluate, and propose innovative solutions for design and architecture problems using analytical and simulation-based approaches.
- Document technical findings, summarize results, and deliver a final presentation to the engineering team.
What you'll need
- Currently pursuing a PhD degree in Electrical Engineering, Computer Science & Engineering, Mathematics, Physics, or a related technical field, having completed at least two years of PhD coursework or research.
- Coursework and/or hands-on research experience in device physics, circuit design, RTL/logic design, design automation, software engineering, RF design, DAC design, ADC design, SerDes design, DSP design, CDR design, PLL design, or clocking circuit design.
- Familiarity with power-efficient and high-performance circuit design methodologies.
- Demonstrated ability to conduct technical research, evaluate alternatives, and apply engineering fundamentals to solve complex problems.
- Interest in advanced communication systems, optical transceivers, mixed-signal circuits, and high-speed interconnect technologies.
Nice to have
- Experience using simulation, modeling, or design tools to analyze and validate engineering designs.
Skills: SerDes, optical transceivers, silicon design, architecture modeling, high-speed interconnect
This role has been open 33 days — well below the 78-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
241
|
Median days open
78 d
|
Median salary
$176k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (241 roles · 47 employers) |
|---|---|---|
| Open roles in this specialty | 29 | 241 |
| Open roles in the wider Analog & Mixed-Signal family | 37 | 1412 · 104 employers |
| Median days open | 36 d | 78 d (−42 d vs this employer) |
| Median salary (USD postings) | — | $176k |
Skills observed across this category: SerDes, optical transceivers, silicon design, architecture modeling, high-speed interconnect
Who's hiring in this category
- Synopsys · 31 open roles · median 30 d
- AMD (this employer) · 30 open roles · median 39 d
- Cadence Design Systems · 19 open roles · median 188 d
- Qualcomm · 19 open roles · median 57 d
- Micron Technology · 14 open roles · median 53 d
- Apple · 12 open roles · median 16 d
How we counted: 241 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 47 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.