VLSI Physical Design / APR Engineer - Taiwan Hsinchu, Taiwan
Originally posted 20 July 2026 by the employer — open 59 days.
About the role
This role is responsible for implementing and optimizing the layout of integrated circuits (ICs) from netlist to GDSII, ensuring electrical performance, area, and power (PPA) goals are met.
What you'll do
- Derive full-chip and block-level physical design from netlist to tape-out (netlist to GDSII).
- Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and layout verifications.
- Sign-off on signal integrity, power integrity, reliability, and manufacturability through static timing analysis (STA), IR drop analysis, EM analysis, and physical verification (DRC/LVS/DFM).
- Analyze, optimize, and resolve congestion, timing, power integrity, and signal integrity issues.
- Create and maintain physical design automation Tcl scripts and flows development for design implementation.
- Interface with EDA tool vendors and foundries to ensure design compliance and manufacturability.
What you'll need
- Master degree majoring in EE/CE/CS related fields.
- At least 2 years of experience in VLSI physical design.
- Solid skill sets of one of Cadence/Synopsys/Mentor EDA tools.
- Experience in design methodology, flow deployment/refinement, and problem solving.
Nice to have
- Experience in tapeout with multi-million gates count SOC design, 10/7/5/3nm design experience.
- Familiar with Perl/TCL scripting.
- Proficiency in speaking and writing English.
Skills: SystemVerilog/UVM, verification plans, testbenches, coverage models, debug
This role has been open 59 days — slightly above the 56-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1122
|
Median days open
56 d
|
Median salary
$192k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Ambarella | All employers we track in this specialty (1122 roles · 92 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 1122 |
| Open roles in the wider Digital Design & Verification family | 9 | 3007 · 114 employers |
| Median days open | 63 d | 56 d (+7 d vs this employer) |
| Median salary (USD postings) | — | $192k |
Skills observed across this category: SystemVerilog/UVM, verification plans, testbenches, coverage models, debug
Who's hiring in this category
- Qualcomm · 104 open roles · median 53 d
- AMD · 99 open roles · median 33 d
- NVIDIA · 90 open roles · median 65 d
- Micron Technology · 56 open roles · median 96 d
- Synopsys · 54 open roles · median 23 d
- SiFive · 51 open roles · median 44 d
How we counted: 1122 open Design Verification (Design Verification) roles from 92 employers tracked in the SemiconductorJobs index, counted 17 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.