VLSI CAD Timing Intern, Applied AI - Summer 2027
Originally posted 29 October 2026 by the employer.
About the role
This role focuses on end-to-end solution development spanning data generation, model training, orchestration, and agentic automation for timing and constraint analysis workflows. You will work on building systems that learn from sign-off data, reason across flows, and assist engineers in achieving closure.
What you'll do
- Support static timing analysis (STA) flows using industry tools like PrimeTime and Tempus for advanced ASIC designs.
- Develop and automate timing, constraints, and QoR validation flows using scripting and data-driven methods.
- Analyze timing reports, constraints, and design data across corners and modes to improve closure predictability.
- Collaborate with CAD, physical design, and methodology engineers on timing sign-off strategies.
- Contribute to AI- or analytics-assisted approaches for timing analysis, constraint checking, or flow optimization.
- Explore how physical effects, including IR drop, crosstalk, aging, and thermal impact, influence timing and design decisions.
What you'll need
- Current enrollment in a Master’s or PhD program in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Coursework or academic knowledge in VLSI/ASIC design, digital circuits, or computer architecture.
- Exposure to applying agentic AI to back-end VLSI tasks such as floorplanning, timing closure, or physical verification.
- Familiarity with the basics of static timing analysis, constraints, or digital design flows.
- Knowledge in scripting or programming, with Python preferred.
- Experience working with data, reports, and technical problem-solving in complex systems.
Nice to have
- Academic projects, research, or internships related to VLSI, physical design, STA, or EDA tools.
- Exposure to TCL.
- Exposure to machine learning, data analysis, or AI concepts applied to engineering problems.
- Experience automating workflows, analyzing large datasets, or contributing to technical tools or open-source projects.
Skills: STA, static timing analysis, PrimeTime, Tempus, applied AI, Python
More semiconductor jobs: NVIDIA jobs · EDA tools engineer jobs · California jobs
This role has been open 0 days — well below the 30-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · AI EDA Design
|
Open roles in category
77
|
Median days open
30 d
|
Category median salary (all employers)
$211k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (77 roles · 27 employers) |
|---|---|---|
| Open roles in this specialty | 11 | 77 |
| Open roles in the wider Physical Implementation family | 80 | 1536 · 112 employers |
| Median days open | 30 d | 30 d (same as this employer) |
| Median salary (USD postings) | — | $211k |
Skills observed across this category: STA, static timing analysis, PrimeTime, Tempus, applied AI, Python
Who's hiring in this category
- NXP Semiconductors · 10 open roles · median 88 d
- NVIDIA (this employer) · 9 open roles · median 36 d
- Keysight Technologies · 7 open roles · median 30 d
- Synopsys · 6 open roles · median 8 d
- Cadence Design Systems · 5 open roles · median 83 d
- Qualcomm · 4 open roles · median 29 d
How we counted: 77 open EDA/CAD Engineering (AI EDA Design) roles from 27 employers tracked in the SemiconductorJobs index, counted 30 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.