Verification Lead (Lead DV) - San Jose, United States
Originally posted 24 June 2026 by the employer.
Lumilens is building critical photonics infrastructure with a focus on chip-to-chip optical interconnects and scalable photonic engines.
About the role
You will own end-to-end verification for a first-of-its-kind chiplet, defining the methodology before RTL development.
What you'll do
- Develop the full DV strategy, including verification plan, coverage model, UVM architecture, and signoff criteria.
- Establish regression/CI infrastructure and nightly runs.
- Verify in-house engines against an algorithmic golden model, with programmable error injection and error-pattern coverage.
- Bring up and own the hardware-assisted verification methodology, using emulation or FPGA prototyping.
- Ensure UCIe VIP and compliance, including link-training, loopback, lane-repair scenarios, and bit-exact transparency.
- Conduct performance and throughput verification.
- Implement UVM register verification, firmware co-simulation, and boot flows on the MCU subsystem.
- Perform mixed-signal co-simulation for digital front end against behavioral analog/mixed-signal models.
- Lead and grow the DV team across various functional areas.
What you'll need
- 10+ years ASIC/SoC verification experience, with team leadership on at least one complex SoC from plan to tapeout.
- Proven leadership verifying large, complex digital SoCs / subsystems, including interconnect fabric and full-chip closure.
- Expertise in UVM/SystemVerilog, coverage-driven verification, and constrained-random methodology.
- Hands-on experience with hardware-assisted verification, such as emulation (Palladium/Veloce) and/or FPGA prototyping (HAPS/Protium).
- Comfort with mixed-signal verification (Verilog-AMS or SV real models).
- Experience with regression/CI at scale (grid, triage automation) and rigorous coverage closure.
Nice to have
- High-speed SerDes, PAM4, or FEC/coding (Reed-Solomon) verification experience.
- UCIe, PCIe/CXL, Ethernet, UALink or comparable die-to-die / link-layer VIP and compliance experience.
- NIC Cards, Ethernet/IB Switches, Cache-coherency verification (multi-core / coherent fabric).
- Low-power/UPF and gate-level simulation methodology.
- Performance-verification methodology.
- Formal verification for control/interlock logic; portable-stimulus.
Skills: UVM/SystemVerilog, coverage-driven verification, hardware-assisted verification, mixed-signal co-simulation, UCIe
This role has been open 73 days — slightly above the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1202
|
Median days open
65 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Lumilens | All employers we track in this specialty (1202 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 1202 |
| Open roles in the wider Digital Design & Verification family | 8 | 3201 · 115 employers |
| Median days open | 73 d | 65 d (+8 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: UVM/SystemVerilog, coverage-driven verification, hardware-assisted verification, mixed-signal co-simulation, UCIe
Who's hiring in this category
- Qualcomm · 110 open roles · median 39 d
- AMD · 96 open roles · median 51 d
- NVIDIA · 84 open roles · median 59 d
- Synopsys · 64 open roles · median 33 d
- SiFive · 55 open roles · median 75 d
- Cadence Design Systems · 50 open roles · median 117 d
How we counted: 1202 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.