Verification Engineer - Palo Alto, United States
$160,000 - $240,000 USD yearly
Originally posted 16 October 2026 by the employer.
About the role
This role is responsible for ensuring the functionality, correctness, and quality of complex digital designs across ASIC and FPGA platforms. Focus areas include building verification environments, executing coverage-driven verification plans, and partnering with RTL design engineers through verification closure.
What you'll do
- Develop, implement, and maintain RTL verification environments using UVM or equivalent methodologies. - Create and execute coverage-driven verification plans aligned with design specifications. - Develop directed and constrained-random test cases, sequences, reusable verification components, and SystemVerilog Assertions (SVA). - Analyze simulation results, debug complex design issues, and perform root-cause analysis with RTL design engineers. - Implement and track functional and code coverage to drive verification closure. - Automate regression testing and enhance verification infrastructure using Python and scripting.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. - 7+ years of experience in digital design verification. - Proficiency in SystemVerilog, UVM, and Python. - Hands-on experience with industry-standard EDA tools (e.g., Synopsys VCS, Siemens/Mentor Questa, Cadence Xcelium). - Experience verifying standard bus and interconnect protocols such as AXI, AXI-S, and APB. - Experience with high-speed communication protocols including PCIe, Ethernet (10G/40G/100G), SPI, and I²C.
Nice to have
- Experience with formal verification techniques and tools. - Experience verifying processor subsystems or SoC-level designs.
Skills: RTL verification environments, UVM, SystemVerilog, coverage-driven verification, EDA tools
This role has been open 11 days — well below the 67-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1268
|
Median days open
67 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Delos Data | All employers we track in this specialty (1268 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 1268 |
| Open roles in the wider Digital Design & Verification family | 3 | 3359 · 116 employers |
| Median days open | 11 d | 67 d (−56 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: RTL verification environments, UVM, SystemVerilog, coverage-driven verification, EDA tools
Who's hiring in this category
- Qualcomm · 120 open roles · median 46 d
- NVIDIA · 93 open roles · median 66 d
- AMD · 92 open roles · median 56 d
- Synopsys · 67 open roles · median 42 d
- SiFive · 56 open roles · median 80 d
- Cadence Design Systems · 50 open roles · median 132 d
How we counted: 1268 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.