Verification Engineer II - Austin (Oakhill, Office), United States
Originally posted 11 June 2026 by the employer.
About the role
This position is within the MME MCU/MPU Digital IP team verifying digital IPs for automotive and advanced microcontroller applications.
What you'll do
- Define and execute verification plans and develop verification testbenches. - Develop testbench components such as drivers, monitors, and scoreboards, and leverage advanced UVM VIPs. - Develop directed and constrained-random stimulus and maintain SystemVerilog assertions (SVA). - Analyze RTL, functional coverage, and assertion coverage results, and define functional coverage models. - Apply formal verification methodologies and perform failure reproduction and root-cause analysis. - Provide technical leadership, guide complex verification challenges, and mentor a small team of engineers.
What you'll need
- BSEE with 2-5 years of semiconductor industry experience, MSEE with 3+ years of experience, or PhD with 1+ years of experience. - Strong expertise in Verilog and SystemVerilog. - Experience with OVM/UVM and class-based verification methodologies. - Experience with formal verification methodologies. - Knowledge of protocols such as DDR, PCIe, or AMBA (CHI, ACE, AXI). - Scripting proficiency in Python, Perl, and UNIX/Linux. - Familiarity with functional and code coverage methodologies.
Nice to have
- Experience with VHDL. - Familiarity with major simulation and debug tools. - Experience leveraging AI/LLM-based approaches to improve engineering efficiency.
Skills: UVM, SystemVerilog, testbench, functional coverage, formal verification
This role has been open 122 days — well above the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1241
|
Median days open
65 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NXP Semiconductors | All employers we track in this specialty (1241 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 45 | 1241 |
| Open roles in the wider Digital Design & Verification family | 131 | 3298 · 115 employers |
| Median days open | 94 d | 65 d (+29 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: UVM, SystemVerilog, testbench, functional coverage, formal verification
Who's hiring in this category
- Qualcomm · 115 open roles · median 42 d
- AMD · 94 open roles · median 52 d
- NVIDIA · 85 open roles · median 64 d
- Synopsys · 66 open roles · median 38 d
- SiFive · 55 open roles · median 80 d
- Cadence Design Systems · 52 open roles · median 122 d
How we counted: 1241 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.