VC Formal Staff Application Engineer
Originally posted 20 September 2026 by the employer — open 1 day.
About the role
This role involves leading the technical deployment of VC Formal at customer sites and optimizing formal testbench modeling for complex SoC and IP designs.
What you'll do
- Lead technical deployment of VC Formal at customer sites, assessing verification environments and recommending formal methodologies.
- Analyze customer design blocks to identify candidates for formal property checking, sequential equivalence, connectivity checking, and formal coverage analysis.
- Diagnose root causes of tool performance issues and design complexity bottlenecks, then optimize formal testbench modeling to achieve proof closure.
- Develop and deliver technical training on VC Formal features, product updates, and formal verification best practices.
- Work with Synopsys R&D teams to communicate customer priorities and technical requirements that influence the product roadmap.
- Apply formal verification across data path logic, math function proofs, sequential equivalence checking, and formal coverage closure.
What you'll need
- 4 to 8 years of hands-on experience applying formal verification in semiconductor design or verification roles.
- Deep expertise in formal property checking, including writing assertions, constraints, and assumptions for complex digital designs.
- Proven experience with sequential equivalence checking, formal coverage analysis, and connectivity checking methodologies.
- Strong understanding of formal verification theory, including state space exploration, abstraction techniques, and proof convergence strategies.
- Experience diagnosing and resolving formal tool performance issues and testbench modeling optimization.
- Ability to assess customer verification environments and recommend tailored formal solutions.
Skills: formal verification, VC Formal, property checking, sequential equivalence, testbench modeling
This role has been open 0 days — well below the 60-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1136
|
Median days open
60 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (1136 roles · 94 employers) |
|---|---|---|
| Open roles in this specialty | 62 | 1136 |
| Open roles in the wider Digital Design & Verification family | 131 | 3020 · 114 employers |
| Median days open | 16 d | 60 d (−44 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: formal verification, VC Formal, property checking, sequential equivalence, testbench modeling
Who's hiring in this category
- Qualcomm · 103 open roles · median 55 d
- AMD · 101 open roles · median 33 d
- NVIDIA · 89 open roles · median 67 d
- Synopsys (this employer) · 58 open roles · median 22 d
- Micron Technology · 56 open roles · median 100 d
- SiFive · 52 open roles · median 48 d
How we counted: 1136 open Design Verification (Design Verification) roles from 94 employers tracked in the SemiconductorJobs index, counted 21 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.