Transceivers & Protocol IP Application Engineer - San Jose, California, United States

Originally posted 26 August 2026 by the employer.

This role focuses on supporting customers with Altera high-speed transceiver PHYs and protocol IP solutions.

About the role

This role involves supporting customers and partners in successfully adopting Altera FPGA transceiver and protocol IP solutions, serving as a technical advisor throughout the design cycle.

What you'll do

• Provide expert technical guidance on Altera high-speed transceiver PHYs and protocol IP, including architecture, IP configuration, clocking, reset, PLL/CDR behavior, and system integration.
• Support customer designs using protocols such as Ethernet, PCIe, JESD204B/JESD204C, CPRI/eCPRI, Interlaken, DisplayPort, HDMI, SerialLite, and PMA/FEC Direct PHY configurations.
• Review customer system architectures, schematics, constraints, RTL, IP parameterization, simulation results, timing reports, and hardware measurements.
• Reproduce and isolate customer issues using Quartus Prime, System Console, Signal Tap, Transceiver Toolkit, simulation environments, and laboratory equipment.
• Own technical cases from initial analysis through resolution, maintaining clear problem statements, evidence, and customer updates.
• Develop scripts, test collateral, reference designs, and automation in Python, Tcl, or Bash to improve debug efficiency and customer adoption.

What you'll need

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
• Professional experience in FPGA applications, high-speed digital design, ASIC/FPGA validation, protocol IP development, or technical customer support.
• Hands-on experience with FPGA design flows and hardware debugging using Quartus Prime or a comparable FPGA development environment.
• Working knowledge of high-speed serial interfaces, transceiver PHY concepts, clocking, PLLs, CDRs, resets, equalization, link training, and signal-integrity fundamentals.
• Experience reading and debugging RTL, IP configuration files, timing constraints, simulation waveforms, register maps, and hardware logs.
• Proficiency in at least one hardware description language, such as Verilog, SystemVerilog, or VHDL.
• Scripting or software-development experience in Python, Tcl, Bash, C, or C++.

Nice to have

• Experience with Altera Agilex, Stratix, Arria, or Cyclone FPGA families and associated transceiver tiles or PHY architectures.
• Knowledge of Ethernet MAC/PCS/FEC, PCIe, JESD204, CPRI/eCPRI, Interlaken, DisplayPort, HDMI, or other high-speed protocol IP.
• Experience with Quartus Prime Pro, Platform Designer, System Console, Signal Tap, Transceiver Toolkit, ModelSim, Questa, or similar EDA and debug tools.
• Experience performing board-level bring-up, eye-diagram or BER analysis, loopback testing, protocol analysis, or lab-based transceiver characterization.
• Experience creating customer-facing documentation, training material, application notes, reference designs, or design examples.
• Willingness to travel occasionally for customer meetings, workshops, design reviews, or hardware bring-up support.

Skills: transceiver PHYs, protocol IP, FPGA design, hardware debugging, customer support