The Principal Test Engineer - Security and Provisioning - Austin, Texas, United States
$249,900 - $338,100 USD yearly
Originally posted 16 July 2026 by the employer.
Deploy secure provisioning flows, eFuse/OTP programming, and lifecycle state transitions on Advantest 93K platforms.
About the role
The Principal Test Engineer – Security and Provisioning is responsible for defining, developing, validating, and deploying secure provisioning flows for semiconductor manufacturing on ATE. This role owns manufacturing execution across wafer sort, final test, SLT, and high-volume manufacturing, covering security lifecycle transitions, eFuse/OTP programming, secure debug control, and device identity provisioning.
What you'll do
- Own the end-to-end ATE provisioning strategy for secure manufacturing flows, including lifecycle state transitions, secure boot enablement, device identity, debug lock/unlock policy, and production fuse programming. - Define and implement manufacturing fuse and provisioning flows, including fuse write, readback, verify, margin read, error handling, retry limits, binning, audit logging, and clear pass/fail criteria. - Partner with Design, Security Architecture, Firmware, Product Engineering, and Manufacturing teams to ensure fuse maps, access controls, provisioning requirements, and debug policies are deterministic for ATE execution. - Work with DV teams to validate provisioning sequences, security blobs, fuse programming models, lifecycle state transitions, negative/error scenarios, and security state-machine behavior before silicon execution. - Develop, simulate, validate, and debug Advantest 93K test methods, digital patterns, datalogging, and production flows for secure provisioning, fuse programming, and post-provisioning integrity checks. - Establish production controls and documentation to prevent over-fusing, incorrect lifecycle transitions, partial provisioning, duplicate programming, wrong-blob usage, or unauthorized debug enablement across CP, FT, SLT, and HVM.
What you'll need
- 10+ years of experience in semiconductor manufacturing, ATE test development, product engineering, production test, or silicon bring-up for complex SoCs or advanced semiconductor devices. - Hands-on experience with Advantest 93K ATE test development, including SmarTest 7 / SmarTest 8, digital patterns, STIL/pattern generation, test methods, debug flows, datalogging, binning, and production test integration. - Experience with eFuse, OTP, non-volatile fuse programming, fuse controllers, lifecycle controllers, JTAG indirect access, readback/verify flows, margin validation, and fuse programming controls. - Prior experience with security lifecycle transitions, secure debug states, device provisioning, key/certificate/blob handling, secure boot enablement, debug authentication, DICE, attestation, Root-of-Trust, RSE, Caliptra, or equivalent secure manufacturing flows. - Understanding of fuse maps, security registers, JTAG/DAP/APB/AXI access paths, manufacturing access restrictions, provisioning appliances, and security/debug infrastructure requirements. - Experience collaborating with DV and design teams to validate test sequences, provisioning blobs, lifecycle state machines, fuse models, negative/error scenarios, and silicon-to-ATE correlation before production release. - Understanding of wafer sort, final test, SLT, HVM release, production quality controls, traceability, data integrity, and manufacturing guardrails.
This role has been open 96 days — well below the 112-day median for Silicon Test Engineering roles.
Silicon Test Engineering · Silicon Validation
|
Open roles in category
193
|
Median days open
112 d
|
Median salary
$140k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Arm Holdings | All employers we track in this specialty (193 roles · 58 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 193 |
| Open roles in the wider Silicon Validation & Test family | 16 | 2229 · 113 employers |
| Median days open | 96 d | 112 d (−16 d vs this employer) |
| Median salary (USD postings) | — | $140k |
Who's hiring in this category
- Teradyne · 13 open roles · median 120 d
- Renesas Electronics · 12 open roles · median 102 d
- Qualcomm · 11 open roles · median 113 d
- onsemi · 10 open roles · median 135 d
- Infineon Technologies · 9 open roles · median 117 d
- Marvell Technology · 9 open roles · median 117 d
How we counted: 193 open Silicon Test Engineering (Silicon Validation) roles from 58 employers tracked in the SemiconductorJobs index, counted 20 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.