Testsite Automation Layout Designer - IND - Karnataka - Bengaluru - North, India
Originally posted 4 August 2026 by the employer.
About the role
This role involves leading the end-to-end execution of technology development test chips from device-level test structures through tapeout and mask ordering.
What you'll do
- Lead the end-to-end layout implementation of technology development test chips, including device test structures, circuit test vehicles, tapeout, and mask order execution. - Develop custom PCells and layout automation solutions using Cadence SKILL scripting to improve design productivity and quality. - Develop RF, analog, and mixed-signal layout solutions that support technology development, characterization, and qualification activities. - Collaborate with device, process, and modeling teams to define, validate, and optimize design rules, layout methodologies, and technology enablement strategies. - Drive continuous improvement of PDK quality, design rules, layout productivity, and design automation capabilities. - Evaluate and resolve layout, manufacturability, reliability, and yield challenges during technology development and productization phases.
What you'll need
- Minimum 10 years of experience in layout design, layout automation, and semiconductor technology development. - BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related discipline. - Expert level proficiency in Cadence SKILL programming with proven experience developing complex layout automation frameworks, custom PCells, and productivity-enhancing design tools. - Hands-on experience with Cadence Virtuoso, custom layout design, PCell development, layout verification methodologies, and automation framework development for semiconductor testsite. - Understanding of semiconductor process technologies, design rules, manufacturability, reliability, and yield considerations. - Experience with test-chip development, DRC/LVS closure, tapeout execution, and mask release processes. - Familiarity with PDK development, design automation, and technology enablement methodologies.
Skills: RF/Analog layout design, CMOS technologies, Cadence Virtuoso, PDK quality, test chip tapeouts
This role has been open 95 days — well above the 51-day median for RF/Wireless Engineering roles.
RF/Wireless Engineering · RF Frontend
|
Open roles in category
265
|
Median days open
51 d
|
Median salary
$162k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | GlobalFoundries | All employers we track in this specialty (265 roles · 34 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 265 |
| Open roles in the wider Analog & Mixed-Signal family | 13 | 1400 · 106 employers |
| Median days open | 95 d | 51 d (+44 d vs this employer) |
| Median salary (USD postings) | — | $162k |
Skills observed across this category: RF/Analog layout design, CMOS technologies, Cadence Virtuoso, PDK quality, test chip tapeouts
Who's hiring in this category
- QORVO · 46 open roles · median 35 d
- Skyworks · 41 open roles · median 40 d
- Keysight Technologies · 24 open roles · median 174 d
- Qualcomm · 24 open roles · median 102 d
- Apple · 20 open roles · median 19 d
- Analog Devices · 12 open roles · median 57 d
How we counted: 265 open RF/Wireless Engineering (RF Frontend) roles from 34 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.