Originally posted 23 July 2026 by the employer.
About the role
Etched is seeking a Test Technical Program Manager to drive manufacturing test strategy and execution across new product introduction and mass production for transformer-specific AI systems. The role oversees manufacturing test development from early architecture and test strategy through factory deployment, production ramp, and yield optimization across board-level, subsystem, and system-level assemblies.
What you'll do
- Drive end-to-end execution of manufacturing test programs across prototype, EVT, DVT, PVT, and mass production builds. - Partner with hardware, firmware, software, systems, validation, and manufacturing engineering teams to define manufacturing test strategy, milestones, and deliverables. - Coordinate development and deployment of board-level, subsystem, and system-level manufacturing test solutions across L6, L10, and L11 assemblies. - Partner with contract manufacturers and FATP partners to deploy, validate, and scale manufacturing test processes globally. - Track manufacturing test readiness, station bring-up, throughput, capacity, coverage, and factory deployment status for assigned programs. - Drive manufacturing test yield improvements, failure analysis, retest reduction, and continuous optimization of factory test processes.
What you'll need
- 7+ years of experience in hardware test engineering, with experience transitioning into a Technical Program Management role. - Experience managing manufacturing test programs for complex hardware systems from development through production. - Strong understanding of manufacturing development phases including EVT, DVT, PVT, and production ramp. - Experience working with contract manufacturers, FATP partners, or ODM/OEM manufacturing organizations. - Understanding of manufacturing test concepts including test coverage, station architecture, fixture development, automation, yield analysis, and failure diagnostics. - Willingness to work in-person from the San Jose office and travel internationally to manufacturing partners as needed.
Nice to have
- Experience developing manufacturing test for AI servers, accelerator systems, networking hardware, storage systems, or other high-performance compute platforms. - Familiarity with board-level test, system-level test, boundary scan, functional test, burn-in, HASS/HALT, or factory automation. - Experience with automated test equipment, test software frameworks, fixture development, or manufacturing diagnostics. - Experience analyzing manufacturing yield, failure Pareto, and test escape data to improve product quality. - Experience working closely with ASIC, firmware, systems, validation, reliability, or hardware engineering teams.
This role has been open 88 days — well below the 111-day median for Silicon Test Engineering roles.
Silicon Test Engineering · Silicon Validation
|
Open roles in category
197
|
Median days open
111 d
|
Median salary
$140k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Etched | All employers we track in this specialty (197 roles · 58 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 197 |
| Open roles in the wider Silicon Validation & Test family | 10 | 2227 · 113 employers |
| Median days open | 166 d | 111 d (+55 d vs this employer) |
| Median salary (USD postings) | — | $140k |
Who's hiring in this category
- Teradyne · 14 open roles · median 113 d
- Renesas Electronics · 13 open roles · median 101 d
- Qualcomm · 11 open roles · median 112 d
- onsemi · 10 open roles · median 134 d
- Infineon Technologies · 9 open roles · median 116 d
- Marvell Technology · 9 open roles · median 116 d
How we counted: 197 open Silicon Test Engineering (Silicon Validation) roles from 58 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.