Test Manager | PADC - Tucson, AZ, United States
Originally posted 24 September 2026 by the employer.
The Precision Analog to Digital Converters team is seeking a Test Manager to manage the planning, development, and implementation of procedures for ADC testing and evaluation.
About the role
As Test Manager, you will manage the planning, development, and implementation of procedures for the testing and evaluation of Analog to Digital Converters (ADCs).
What you'll do
- Lead a test engineering team and drive test strategies for precision 24-bit ADCs.
- Optimize production test programs, including test time reduction activities, and yield improvement.
- Develop and drive TI technology for Design for Test (DFT), design verification, failure analysis and qualification of products.
- Translate defect-driven test suites to production test solutions that validate spec performance.
- Create and implement highly optimized tester agnostic and design centric test methods.
- Analyze test data to understand and resolve problems.
What you'll need
- Bachelors in Electrical Engineering.
- 5+ years of relevant experience in analog testing.
- 2+ years experience of leadership experience.
- Proven history of technical accomplishment, planning, coordinating, and executing on multiple projects simultaneously in test development and test cost reduction activities.
- Breadth of test platform and test technologies.
- Advanced level of understanding and use of Advantest and/or Teradyne/Eagle ATE.
Nice to have
- Track record of innovation in test methods.
- Experience with ADC test/validation methodologies and debugging.
- Demonstrated expertise in hardware debugging and failure analysis.
This role has been open 16 days — below the 25-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
526
|
Median days open
25 d
|
Median salary
$169k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Texas Instruments | All employers we track in this specialty (526 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 22 | 526 |
| Open roles in the wider Silicon Validation & Test family | 98 | 2196 · 111 employers |
| Median days open | 19 d | 25 d (−6 d vs this employer) |
| Median salary (USD postings) | — | $169k |
Who's hiring in this category
- Teradyne · 68 open roles · median 22 d
- Renesas Electronics · 39 open roles · median 25 d
- Infineon Technologies · 38 open roles · median 34 d
- AMD · 28 open roles · median 37 d
- Micron Technology · 28 open roles · median 31 d
- Qualcomm · 25 open roles · median 24 d
How we counted: 526 open Silicon Test Engineering (DFT Test) roles from 75 employers tracked in the SemiconductorJobs index, counted 10 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.