Test Architect (CTD; Austin, TX)
$155,000 - $248,100 USD yearly
Originally posted 22 September 2026 by the employer.
About the role
This role leads test engineering activities for strategic semiconductor test customers, translating device requirements into production-ready test solutions. It involves defining test strategies, guiding implementation, and resolving product and production issues.
What you'll do
- Serve as the test architecture for assigned strategic customers, clarifying product test requirements and technical tradeoffs.
- Define end-to-end test strategies covering test content, coverage, insertions, instrumentation, multisite execution, and production release.
- Guide implementation through feasibility studies, prototypes, test plan reviews, silicon debug, characterization, and resolution of yield, quality, or production issues.
- Design for accurate and repeatable measurement, establishing approaches for calibration, uncertainty, limits, guardbands, and correlation.
- Optimize the complete test solution across coverage, quality, test time, throughput, hardware utilization, and cost.
- Develop reusable test methods, patterns, flows, design guidelines, validation assets, and debug practices.
- Coach test and software engineers in architecture and disciplined test development.
- Represent Teradyne in customer workshops, architecture reviews, and escalations.
What you'll need
- Bachelor degree in Electrical Engineering, Computer Engineering, Applied Physics, or equivalent practical experience.
- At least 7 years of semiconductor test engineering experience, including defining test strategy or leading technical direction for complex products.
- Strong knowledge of automated test equipment, semiconductor devices, test methods, instrument capabilities, and production test constraints.
- Practical experience with test development, silicon bring-up, characterization, correlation, multisite validation, and test time optimization.
- Ability to translate product requirements and failure risks into test coverage, evaluate alternatives, and explain tradeoffs.
- Experience leading through technical influence, collaboration, and mentorship across customer, product, hardware, software, and manufacturing teams.
Nice to have
- Master degree in Electrical Engineering, Computer Engineering, Applied Physics, or a related discipline.
- Deep experience with digital, power, protocol-aware, memory, RF, or mixed-signal semiconductor test.
- Experience with DFT, scan, BIST, pattern generation, device characterization, statistical limit setting, yield analysis, or adaptive test.
- Experience architecting test solutions for advanced packaging, chiplets, high site count, high power, high speed interfaces, or constrained production environments.
This role has been open 19 days — below the 26-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
522
|
Median days open
26 d
|
Median salary
$169k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Teradyne | All employers we track in this specialty (522 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 67 | 522 |
| Open roles in the wider Silicon Validation & Test family | 83 | 2197 · 111 employers |
| Median days open | 24 d | 26 d (−2 d vs this employer) |
| Median salary (USD postings) | — | $169k |
Who's hiring in this category
- Teradyne (this employer) · 67 open roles · median 23 d
- Renesas Electronics · 39 open roles · median 26 d
- Infineon Technologies · 38 open roles · median 35 d
- Micron Technology · 28 open roles · median 32 d
- AMD · 27 open roles · median 38 d
- Qualcomm · 24 open roles · median 26 d
How we counted: 522 open Silicon Test Engineering (DFT Test) roles from 75 employers tracked in the SemiconductorJobs index, counted 11 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.