Technical Staff Engineer - Hardware - CA - San Jose - 3870 N. First St, United States
$91,000 - $232,000 USD yearly
Originally posted 22 February 2026 by the employer. Relisted by the employer on 9 October 2026.
About the role
The Frequency and Time Systems (FTS) development team is seeking an experienced circuit design engineer to help develop network timing equipment, including PTP grandmasters and NTP servers. This role spans analog and digital circuit design, including DDR memories, FPGAs, microprocessors, and MCUs, with ownership from architecture and schematic design through PCB bring-up, validation, and sustaining support.
What you'll do
- Define new product features, requirements, and system-level tradeoffs with cross-functional teams. - Develop analog and digital circuit designs and create schematics using CAD tools. - Partner with PCB layout engineers on board layout, signal integrity, manufacturability, and design reviews. - Create detailed hardware design documentation, test plans, and maintain design data in the Agile PLM system. - Support software and digital design engineers during board bring-up, driver development, and validation of board-level functions. - Drive hardware development from concept through finished product, including bring-up, validation, release, and sustaining support.
What you'll need
- Bachelor's degree in Electrical Engineering or Computer Engineering/Science. - 12+ years of hands-on circuit design experience across analog and digital circuit design concepts and digital systems architecture. - Hands-on experience using lab equipment such as oscilloscopes, network analyzers, and related test equipment. - Experience with Altium and/or HyperLynx CAD tools. - Experience with high-speed PCB transmission line structures, signal integrity practices, and related design constraints.
Nice to have
- Master's degree in Electrical Engineering or Computer Engineering/Science.
Skills: PCIe 5.0, DDR5, I2C/I3C, schematic capture, signal integrity, hardware debug
This role has been open 222 days — well above the 71-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
247
|
Median days open
71 d
|
Median salary
$191k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Microchip Technology | All employers we track in this specialty (247 roles · 47 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 247 |
| Open roles in the wider Analog & Mixed-Signal family | 33 | 1453 · 106 employers |
| Median days open | 126 d | 71 d (+55 d vs this employer) |
| Median salary (USD postings) | — | $191k |
Skills observed across this category: PCIe 5.0, DDR5, I2C/I3C, schematic capture, signal integrity, hardware debug
Who's hiring in this category
- Synopsys · 34 open roles · median 36 d
- AMD · 27 open roles · median 45 d
- Cadence Design Systems · 21 open roles · median 140 d
- Qualcomm · 21 open roles · median 69 d
- Micron Technology · 13 open roles · median 41 d
- Apple · 12 open roles · median 25 d
How we counted: 247 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 47 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.