Technical Staff Engineer - AMS Verification - AZ - Chandler, United States
Originally posted 14 June 2026 by the employer.
System-level AMS verification and PI/SI simulation across chiplet boundaries and 12nm digital nodes.
About the role
Responsible for system-level Analog Mixed-Signal (AMS) verification and Power Integrity (PI/SI) for SoCs and chiplet-based platforms. The position integrates analog IP in mature nodes with advanced digital nodes including 12nm and beyond.
What you'll do
- Lead and contribute to sub-system and chip-level AMS and SPICE simulations for complex SoCs and multi-die chiplet architectures. - Drive AMS verification across chiplet boundaries, including cross-node integration combining mature analog and 12nm digital designs. - Plan and execute AMS/SPICE simulation strategies, including full-chip and chiplet-level verification. - Perform PI/SI simulations covering the die pad ring, package and interposer for chiplet-based designs, and PCB interfaces. - Analyze power integrity and signal integrity across chiplet interfaces and multiple power domains while developing AMS and PI/SI flows. - Partner with validation teams on silicon bring-up, debug, and simulation-to-silicon correlation.
What you'll need
- Bachelor’s or Master’s degree in electrical engineering or equivalent with 14+ years of experience. - Proven experience in AMS verification for advanced SoCs, including exposure to 12nm nodes or beyond. - Solid understanding of cross-domain interactions and multi-voltage/power domains. - Hands-on experience with Cadence tools (Virtuoso, Spectre, AMS Designer), Questa ADMS / Symphony, and HSPICE or equivalent. - Experience in silicon debug and correlation of simulation results with silicon behavior. - Ability to analyze and interpret chip-level electrical specifications and IO requirements.
Nice to have
- Experience with chiplet architectures or multi-die system integration. - Exposure to die-to-die interfaces and advanced node (12nm and beyond) integration challenges. - Experience in circuit-level debug and modeling.
Skills: AMS verification, PI/SI simulation, chiplet architectures, Spectre, design verification
This role has been open 125 days — well above the 66-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1254
|
Median days open
66 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Microchip Technology | All employers we track in this specialty (1254 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 21 | 1254 |
| Open roles in the wider Digital Design & Verification family | 67 | 3310 · 115 employers |
| Median days open | 73 d | 66 d (+7 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: AMS verification, PI/SI simulation, chiplet architectures, Spectre, design verification
Who's hiring in this category
- Qualcomm · 118 open roles · median 45 d
- AMD · 92 open roles · median 55 d
- NVIDIA · 91 open roles · median 65 d
- Synopsys · 65 open roles · median 41 d
- SiFive · 55 open roles · median 83 d
- Cadence Design Systems · 52 open roles · median 125 d
How we counted: 1254 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.