Technical Program Manager, Silicon Physical Design - Mountain View, CA, United States

Originally posted 15 July 2026 by the employer.

About the role

You will own the cross-functional execution framework for advanced SoC programs from early planning through tapeout. You will drive milestones, dependencies, execution reviews, decision-making forums, risk management, and tapeout readiness across multiple engineering teams.

What you'll do

- Lead end-to-end execution of SoC development programs from concept through production. - Develop playbooks and best practices for program management across the physical design organization for cross-functional deliveries. - Drive issue resolution during pre-silicon execution, tapeout, bring-up, debug, qualification, and yield learning to ensure physical design readiness. - Track technical dependencies, schedule risks, critical path, milestones, tapeout readiness, and silicon bring-up deliverables. - Manage technical risks related to design maturity, IP readiness, verification closure, physical signoff, package/test readiness, and supply chain. - Support silicon planning across performance, power, area, cost, reliability, and manufacturability tradeoffs.

What you'll need

- 10+ years of technical program management, silicon engineering program management, or leading SoC programs through multiple phases of the silicon lifecycle. - Experience managing pre-silicon ASIC development flows, including architecture planning, RTL design, functional verification, synthesis, DFT, physical design, timing closure, signoff, and tapeout. - Experience with pre-silicon validation platforms such as simulation, emulation, FPGA prototyping, or hardware/software co-validation. - Technical fluency in SoC or chiplet design flows covering RTL milestones, DV sign-off, PD handoffs, and silicon bring-up phases. - Proficiency with program management and engineering collaboration tools such as Jira, GitHub, Confluence, Smartsheet, or MS Project.

Nice to have

- Prior hands-on engineering experience in BE PD. - Experience with AI infrastructure, datacenter racks, networking systems, storage systems, or high-power server platforms. - Experience coordinating programs involving high-speed interconnects, liquid-cooled systems, telemetry, diagnostics, or rack-scale validation.

Skills: cross-functional execution, milestones, risk management, tapeout readiness, SoC development