Technical Program Manager, Silicon/Hardware - Mountain View (HQ) or Remote, United States
$250,000 - $600,000 USD yearly
Originally posted 10 September 2026 by the employer.
Developing silicon for high-performance and sustainable GenAI.
About the role
This role involves owning the cross-functional execution framework for advanced Silicon HW programs, from early planning through tapeout.
What you'll do
- Lead end-to-end execution of Silicon HW development programs, from concept through production, driving planning and implementation across cross-functional teams.
- Partner with Architecture, RTL Design, and Design Verification (DV) teams to identify bottlenecks, track coverage metrics, and mitigate risks before they impact the tapeout schedule.
- Define the core operational processes and modes of work for the HW group, building and refining the stage-gate reviews.
- Develop playbooks and best practices for program management across the Silicon HW organization for cross-functional deliveries.
- Support silicon planning across performance, power, area, cost, reliability, and manufacturability tradeoffs.
- Manage technical risks related to schedule, design maturity, IP readiness, verification closure, physical signoff, package/test readiness, and supply chain.
What you'll need
- 15+ years of experience in chip/IC development as an engineer, engineering manager, or technical program manager, with at least 3 years in a technical program manager role.
- Experience leading Silicon HW programs through multiple phases of the silicon lifecycle, with end-to-end chip execution from concept to silicon.
- Experience driving complex cross-functional programs with multiple engineering teams, technical dependencies, external vendors, and tight schedules.
- Technical fluency in SoC or chiplet design flows to understand RTL milestones, DV signoff, Silicon HW handoffs, and silicon bring-up phases.
- Strong technical judgment with the ability to manage tradeoffs across performance, power, area, cost, schedule, quality, and risk.
- Proficiency with program-management and engineering collaboration tools such as Jira, GitHub, Confluence, Smartsheet, MS Project, Google Workspace, or equivalent.
Nice to have
- Experience with AI infrastructure, datacenter racks, networking systems, storage systems, or high-power server platforms.
- Experience coordinating programs involving high-speed interconnects, liquid-cooled systems, telemetry, diagnostics, or rack-scale validation.
- Prior hands-on engineering experience in BE PD.
Skills: tapeout, silicon lifecycle, RTL Design, Design Verification, risk management
This role has been open 36 days — well below the 46-day median for Technical Program Management roles.
Technical Program Management · SOC Architecture
|
Open roles in category
175
|
Median days open
46 d
|
Median salary
$220k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | MatX | All employers we track in this specialty (175 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 175 |
| Median days open | 36 d | 46 d (−10 d vs this employer) |
| Median salary (USD postings) | — | $220k |
Skills observed across this category: tapeout, silicon lifecycle, RTL Design, Design Verification, risk management
Who's hiring in this category
- Qualcomm · 25 open roles · median 46 d
- NVIDIA · 20 open roles · median 34 d
- AMD · 19 open roles · median 25 d
- Synopsys · 14 open roles · median 46 d
- Arm Holdings · 10 open roles · median 83 d
- Astera Labs · 6 open roles · median 67 d
How we counted: 175 open Technical Program Management (SOC Architecture) roles from 49 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.