Technical Program Manager, Hardware - Mountain View, CA, United States
$129,000 - $300,000 USD yearly
Originally posted 12 June 2026 by the employer.
Drive the cross-functional execution of our AI accelerator hardware program.
About the role
This role drives the cross-functional execution of the AI accelerator hardware program, owning schedules, dependencies, and risks across silicon, board/system hardware, and low-level software from architecture through tapeout, bring-up, and scale-out. This position requires technical understanding of the systems-programming layer, including firmware, drivers, and bring-up software, where hardware and software converge.
What you'll do
- Own end-to-end program management for major hardware workstreams: schedule, dependencies, critical path, and risk from architecture through tapeout and silicon bring-up.
- Drive cross-functional execution across silicon (design, DV, physical design, packaging), board/system hardware, and software teams, aligning milestones and clearing dependencies.
- Bridge hardware and the systems-software stack, coordinating firmware, device drivers, and bring-up software that exercises new silicon and boards.
- Run the program operating cadence including planning, milestone tracking, status, risk reviews, and executive communication.
- Identify critical-path risks and drive them to resolution before schedule slips; own tapeout readiness and milestone gating.
- Translate low-level technical blockers (bring-up failures, driver/firmware issues, HW/SW integration bugs) into program decisions and facilitate team triage.
What you'll need
- 5+ years of technical program/project management in hardware, silicon, or deeply technical software, driving complex cross-functional programs to delivery.
- Strong technical fluency to engage with chip-design and software engineers and understand dependencies between RTL, PD, DV, packaging, compiler, runtime, and bring-up.
- Systems-programming background: hands-on C/C++ (and/or Rust), Linux internals, firmware, device drivers, or bring-up software to read code, investigate low-level issues, and earn engineers' trust.
- Demonstrated ownership of schedule, critical path, and risk on a large multi-team program, ideally through a silicon tapeout or comparable hardware milestone.
- Excellent communication and stakeholder management, from IC engineers to executives.
Nice to have
- Silicon program experience through tapeout/bring-up; ASIC/SoC development lifecycle; hardware/software co-development; Jira/Confluence; PMP or Agile; AI/ML or accelerator domain.
Skills: program management, hardware workstreams, silicon tapeout, silicon bring-up, firmware, device drivers
This role has been open 34 days — well below the 47-day median for Technical Program Management roles.
Technical Program Management · SOC Architecture
|
Open roles in category
175
|
Median days open
47 d
|
Median salary
$219k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | DensityAI | All employers we track in this specialty (175 roles · 47 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 175 |
| Median days open | 34 d | 47 d (−13 d vs this employer) |
| Median salary (USD postings) | — | $219k |
Skills observed across this category: program management, hardware workstreams, silicon tapeout, silicon bring-up, firmware, device drivers
Who's hiring in this category
- Qualcomm · 26 open roles · median 50 d
- AMD · 20 open roles · median 28 d
- NVIDIA · 19 open roles · median 47 d
- Synopsys · 14 open roles · median 44 d
- Arm Holdings · 10 open roles · median 81 d
- Apple · 6 open roles · median 65 d
How we counted: 175 open Technical Program Management (SOC Architecture) roles from 47 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.