Technical Director, Packaging Engineering (AI2557) - San Jose, California, United States

Originally posted 5 October 2026 by the employer.

Drive FCBGA and SiP packaging technology development for SiMa.ai MLSoC™ IC roadmap.

About the role

As Technical Director, Packaging Engineering, you will drive high-performance FCBGA and SiP packaging technology development to support the SiMa.ai MLSoC™ IC roadmap from package definition and design through qualification to mass production. This role involves personal ownership of package design and SI/PI for high-speed LPDDR and PCIe interfaces.

What you'll do

• Own package SI/PI for high-speed interfaces, including LPDDR5x/6 DRAM, PCIe Gen5, 10G Ethernet, and MIPI, covering chip–package–board co-design and channel/PDN simulation.
• Lead advanced package development activities from definition and design to mass production, considering interconnects design, thermo-mechanical aspects, quality, reliability, cost, and yield.
• Define and implement FCBGA and SiP packaging strategies for high-speed complex mixed-signal ICs in collaboration with Design, Hardware, and Quality teams.
• Drive OSAT and substrate supplier relationships, including selection, negotiation, capacity, process/material qualification, PCN review, and yield/cost roadmaps.
• Oversee packaging NPI activities, including characterization, qualification (JEDEC, AEC-Q100, board-level reliability), and productization for tier-1 customers, including Automotive.
• Manage package production control, issue resolution, yield/DPPM monitoring, and improvement.

What you'll need

• BS/MS in Electrical Engineering, Mechanical Engineering, Material Science, or related field with 10+ years relevant experience in FCBGA/SiP package design and development.
• Hands-on SI/PI design and simulation of high-speed DRAM (LPDDR5x/6), PCIe (Gen5), UCIe channels and PDN at package and board level using tools such as Ansys HFSS/SIwave, Cadence Sigrity/Clarity, or Keysight ADS, with lab correlation (VNA/TDR, eye measurements).
• Hands-on package substrate design experience: bump/ball map, stack-up, routing, and design-rule trade-offs with substrate vendors (Cadence APD+/SiP Layout or equivalent).
• SiP experience: multi-die and SoC-plus-memory integration, passive integration, and related assembly and test challenges.
• Proven track record driving OSATs and substrate suppliers from package definition through qualification and mass production.
• Automotive package qualification and NPI-to-mass-production experience (AEC-Q100, PPAP).
• Understanding and hands-on experience of complex high-speed mixed-signal SoC High Performance FCBGA packaging development, cost, and quality.
• Proficiency with thermal, mechanical, reliability, and cost trade-offs in package design.
• Experience with FCBGA failure mechanisms and failure analysis.
• Experience with advanced substrate materials with low dielectric constant (Dk), low dielectric loss (Df), and low coefficient of thermal expansion (CTE) at high frequencies.

Nice to have

• Familiarity with 2.5D and Chiplet technologies.
• Package-board co-design for modules and PCIe add-in cards.