Tech Lead– Verification Methodology/CAD - Bengaluru, Karnataka, India
Originally posted 27 August 2026 by the employer.
About the role
This role involves driving verification infrastructure, methodology, automation, and productivity for IP and SoC verification teams. The successful candidate will build scalable verification frameworks and automate workflows, contributing to efficient and reusable methodologies.
What you'll do
- Own and drive verification methodology and infrastructure across projects.
- Develop scalable frameworks for simulation, regression, coverage, debug, and verification signoff.
- Build and maintain verification CAD/automation flows.
- Develop automation scripts and tools using Python, Tcl, Perl, Shell, and/or C++.
- Automate test generation, compilation, regression execution, result collection, and coverage analysis.
- Develop infrastructure for large-scale UVM/SystemVerilog verification environments.
What you'll need
- Strong experience in verification methodology, CAD, and automation.
- Strong programming/scripting skills in Python, Tcl, Perl, Shell, and preferably C/C++.
- Experience with UVM/SystemVerilog verification environments.
- Experience building and maintaining regression infrastructure.
- Knowledge of simulation, lint, CDC/RDC, formal, and coverage tools.
- 6–12 years of experience.
Skills: verification methodology, CAD/automation flows, Python, SystemVerilog/UVM, regression infrastructure
This role has been open 31 days — well below the 83-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
673
|
Median days open
83 d
|
Median salary
$197k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (673 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 673 |
| Open roles in the wider Physical Implementation family | 23 | 1400 · 108 employers |
| Median days open | 91 d | 83 d (+8 d vs this employer) |
| Median salary (USD postings) | — | $197k |
Skills observed across this category: verification methodology, CAD/automation flows, Python, SystemVerilog/UVM, regression infrastructure
Who's hiring in this category
- Cadence Design Systems · 172 open roles · median 151 d
- Synopsys · 56 open roles · median 55 d
- Micron Technology · 41 open roles · median 107 d
- NVIDIA · 41 open roles · median 65 d
- Qualcomm · 35 open roles · median 66 d
- Intel Corporation · 22 open roles · median 29 d
How we counted: 673 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 28 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.