Tech Lead, STA - Hyderabad, Telangana, India
Originally posted 15 September 2026 by the employer — open 0 days.
About the role
This role involves owning top-level timing closure and signoff for AI connectivity silicon. You will drive full-chip Static Timing Analysis strategy across advanced process nodes, specifically 5nm/4nm/3nm and below.
What you'll do
- Own end-to-end top-level Static Timing Analysis signoff across multiple modes, corners, and operating conditions (MMMC) for complex AI connectivity SoCs.
- Drive timing convergence on advanced process nodes from early floorplan through tapeout.
- Define and evolve Static Timing Analysis methodology, SDC strategy, and signoff criteria.
- Develop and automate flows using PrimeTime, PrimeTime SI, and related signoff tools for crosstalk, noise, and IR-aware timing.
- Partner with Physical Design, RTL, DFT, CAD, and Package teams to drive timing-aware design decisions.
- Mentor Static Timing Analysis engineers and review timing reports, ECOs, and signoff collateral.
What you'll need
- Bachelor's degree in Electrical Engineering, Electronics Engineering, or related field.
- 6+ years of hands-on experience in Static Timing Analysis on complex ASIC/SoC designs.
- Proven track record of full-chip top-level Static Timing Analysis signoff on at least one tapeout at advanced nodes (7nm or below).
- Deep expertise with PrimeTime, PrimeTime SI, and SDC constraint development.
- Strong understanding of clocking architectures, CDC, OCV/AOCV/POCV, crosstalk, and IR-aware timing.
- Proficiency in scripting (Tcl, Python, Perl) for Static Timing Analysis flow automation and report analysis.
Nice to have
- Master's degree in Electrical Engineering or related field.
- Experience with high-speed connectivity SoCs (PCIe Gen 6/7, CXL, UALink, or Ethernet).
- Familiarity with hierarchical Static Timing Analysis, ETM/ILM models, and timing budgeting across large partitions.
- Experience with low-power signoff (UPF/CPF), multi-voltage domains, and DVFS timing implications.
Skills: Static Timing Analysis, STA signoff, timing closure, PrimeTime, SDC constraints
This role has been open 0 days — well below the 59-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
611
|
Median days open
59 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (611 roles · 76 employers) |
|---|---|---|
| Open roles in this specialty | 20 | 611 |
| Open roles in the wider Physical Implementation family | 25 | 1411 · 108 employers |
| Median days open | 96 d | 59 d (+37 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: Static Timing Analysis, STA signoff, timing closure, PrimeTime, SDC constraints
Who's hiring in this category
- Qualcomm · 100 open roles · median 39 d
- Broadcom · 39 open roles · median 64 d
- NVIDIA · 37 open roles · median 39 d
- AMD · 31 open roles · median 50 d
- Synopsys · 27 open roles · median 67 d
- Renesas Electronics · 24 open roles · median 49 d
How we counted: 611 open Physical Design (Physical Design) roles from 76 employers tracked in the SemiconductorJobs index, counted 15 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.