Tech Lead Engineer, Design Verification - San Jose, California, United States
$175,500 - $195,000 USD yearly
Originally posted 28 September 2026 by the employer.
Join Astera Labs to deliver robust verification for connectivity silicon enabling rack-scale AI infrastructure, specifically focusing on PCIe and UALink products.
About the role
This role focuses on delivering highly reliable PCIe and UALink connectivity products.
What you'll do
- Develop block- and subsystem-level verification plans from specifications, architecture, and design requirements.
- Define test scenarios, coverage models, checkers, assertions, and scoreboards for complex switching functionality.
- Lead verification planning and execution for assigned features, tracking risks, milestones, and quality metrics.
- Build and enhance reusable UVM-based SystemVerilog testbenches, agents, sequences, monitors, and reference models.
- Create directed, constrained-random, and power-on-reset scenarios spanning PCIe Gen 6/Gen 7, UALink, and UCIe behavior.
- Drive functional and code coverage analysis, identify verification gaps, and close coverage to agreed milestones.
What you'll need
- Experience defining and delivering robust verification for connectivity silicon.
- Ability to build verification strategies for complex switching behavior across high-bandwidth protocols.
- Expertise in UVM-based SystemVerilog testbench development.
- Experience with directed, constrained-random, and power-on-reset scenarios for PCIe Gen 6/Gen 7, UALink, and UCIe.
- Proficiency in debugging simulation failures using waveform analysis, logs, and assertions.
- Capability to drive functional and code coverage analysis, identify verification gaps, and close coverage.
Skills: SystemVerilog, UVM, verification plans, PCIe, UALink
This role has been open 1 day — well below the 63-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1169
|
Median days open
63 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (1169 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 19 | 1169 |
| Open roles in the wider Digital Design & Verification family | 58 | 3109 · 115 employers |
| Median days open | 33 d | 63 d (−30 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: SystemVerilog, UVM, verification plans, PCIe, UALink
Who's hiring in this category
- AMD · 104 open roles · median 39 d
- Qualcomm · 97 open roles · median 53 d
- NVIDIA · 86 open roles · median 70 d
- Synopsys · 62 open roles · median 23 d
- SiFive · 57 open roles · median 56 d
- NXP Semiconductors · 52 open roles · median 76 d
How we counted: 1169 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 29 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.