Tech Lead, Digital Design Engineer - San Jose, California, United States
$175,500 - $195,000 USD yearly
Originally posted 30 September 2026 by the employer.
About the role
This role involves driving front-end digital design for high-performance switch ASICs that enable rack-scale AI infrastructure.
What you'll do
- Define microarchitecture and implement synthesizable RTL for complex switch ASIC blocks.
- Develop front-end design solutions for high-performance networking and server connectivity applications.
- Drive block-level execution through synthesis, timing closure, gate-level simulation, DFT, and GDS delivery.
- Analyze design tradeoffs across performance, power, area, and schedule.
- Partner with design verification engineers to define plans, debug failures, and improve coverage using UVM-based methodologies.
- Support silicon bring-up, lab debug, and root-cause analysis for complex connectivity issues.
What you'll need
- Bachelor’s degree in Electrical Engineering or a related field.
- 5–8 years of experience developing or supporting complex SoC or silicon products for switch ASIC, networking, server, or storage applications.
- Hands-on experience with high-speed protocols, including UALink, UCI, PCIe Gen 6/7, ESUN, and Ethernet.
- Proven front-end digital design experience spanning architecture, RTL, simulation, synthesis, timing closure, gate-level simulation, and DFT.
- Experience owning blocks from architecture through GDS.
- Experience working with Synopsys and/or Cadence design tools and flows.
Nice to have
- Master’s degree in Electrical Engineering or a related field.
- Experience developing or supporting PCIe or Ethernet switch products.
- Familiarity with UVM-based design verification and coverage-driven debug.
- Silicon bring-up and debug experience in small-geometry CMOS technologies at 28nm or below.
- Scripting experience with Python or comparable programming languages.
This role has been open 0 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
982
|
Median days open
62 d
|
Median salary
$183k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (982 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 28 | 982 |
| Open roles in the wider Digital Design & Verification family | 61 | 3086 · 115 employers |
| Median days open | 20 d | 62 d (−42 d vs this employer) |
| Median salary (USD postings) | — | $183k |
Who's hiring in this category
- Qualcomm · 144 open roles · median 58 d
- AMD · 66 open roles · median 66 d
- Synopsys · 66 open roles · median 24 d
- NXP Semiconductors · 52 open roles · median 73 d
- NVIDIA · 49 open roles · median 54 d
- Analog Devices · 45 open roles · median 37 d
How we counted: 982 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.