TD Memory Quality and Reliability Engineer - United States

Originally posted 1 September 2026 by the employer.

This role focuses on post-silicon memory characterization and certification for advanced SRAM, Register File, and fuse array technologies.

About the role

This role drives post-silicon memory characterization, certification, and technology readiness activities for advanced SRAM, Register File (RF), and/or fuse array. The team supports technology certification and PDK release milestones by establishing certification strategies and developing Vccmin models.

What you'll do

• Plan and execute SRAM, RF, and/or Fuse technology certification supporting technology development and certification milestones.
• Drive memory array characterization across multiple operating conditions to evaluate Vmin, Vmax, aging behavior, variability, and design margins.
• Analyze silicon characterization data to identify performance gaps, failure signatures, systematic trends, and technology risks.
• Develop, validate, and maintain silicon-based Vccmin and Vmax predictive models used for technology certification, PDK releases, and product guidance.
• Perform silicon-to-simulation (Sil2Sim) correlation assessments and drive understanding of discrepancies between measured silicon behavior and design predictions.
• Generate certification reports, readiness assessments, and risk projections that support technology deployment decisions.

What you'll need

• Ph.D. in Electrical Engineering, Computer Engineering, Physics or related discipline with 2+ years of semiconductor industry experience OR M.S. in Electrical Engineering, Computer Engineering, Physics, Materials Science, or related discipline with 6+ years of semiconductor industry experience.
• 2+ years of hands-on experience with memory testing.
• 2+ years of experience performing quantitative analysis of large-scale memory or semiconductor datasets using statistical methods such as DOE, SPC, regression analysis, hypothesis testing, or multivariate analysis.
• 2+ years of hands-on experience using JMP and Python for data analysis, statistical modeling, process optimization, automation, or data visualization.

Nice to have

• Experience in memory design, characterization, validation, modeling, product development, quality, reliability, or technology development.
• Strong understanding of SRAM and/or Register File design fundamentals, silicon characterization techniques, and variability analysis.
• Experience developing silicon-based predictive models, statistical distributions, guardbands, and product risk projections.
• Knowledge of Vmin/Vmax characterization methodologies, memory margin assessment, array screening techniques, or design technology co-optimization.
• Experience with silicon-to-simulation correlation (Sil2Sim), SPICE modeling, or design validation.
• Programming experience in Python, JSL, SQL, or data analytics frameworks.

Skills: memory characterization, SRAM, reliability, Vccmin models, technology certification