Systems Solutions Architect
$185,500 - $344,500 USD yearly
Architect compute-centric SoC subsystems for Physical AI using Tensilica DSPs, CPUs, and Neo NPUs.
Originally posted 4 November 2026 by the employer.
About the role
Cadence's SSG Central Applications Engineering team is seeking a Systems Solutions Architect and Technical Lead to define compute-centric solutions for Physical AI. In this role, you will define SoC subsystems for Edge AI and Physical AI applications using Cadence DSPs, CPUs, NPUs, and accelerators, optimizing for power, performance, area, and software flexibility.
What you'll do
- Define and own the system architecture for new hardware subsystems (compute, memory, interconnects, interfaces) and the corresponding software stack (drivers, HAL, compiler runtimes, and middleware).
- Architect solutions using the Cadence SSG IP portfolio, including Tensilica DSPs, CPUs, Neo NPU, application-specific accelerators, interface IP, and memory controllers.
- Partner with performance modeling teams to build cycle-accurate or transaction-level (TLM) simulations of the SoC subsystem, using performance simulation data to identify bottlenecks.
- Deliver architectural specifications to RTL/hardware implementation and software/firmware engineering teams, serving as the bridge to ensure cross-functional alignment.
- Serve as the final authority during system integration, validating that the software stack extracts maximum performance from physical hardware features.
- Build scalable proof-of-concept (PoC) and reference designs, and act as a technical liaison to influence future IP roadmaps based on emerging Physical AI trends.
What you'll need
- 12+ years in an architectural or system engineering role, with a history of architecting complex systems from concept through to production.
- Track record of designing integrated solutions where hardware features are explicitly built to support software mechanics, and vice versa.
- Experience collaborating with or leading performance modeling teams using SystemC, TLM, or custom cycle-accurate simulator infrastructures.
- Experience in Physical AI (robotics, autonomous systems) delivering real-time Imaging and/or Radar (spatial awareness, tracking) and Advanced Audio processing.
- Ability to travel up to 10% of the time, including internationally.
Skills: SoC architecture, Edge AI, SystemC, TLM, DSP, NPU
More semiconductor jobs: Cadence Design Systems jobs · SoC design jobs
This role has been open 0 days — well below the 76-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
490
|
Median days open
76 d
|
Category median salary (all employers)
$230k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (490 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 490 |
| Open roles in the wider Digital Design & Verification family | 121 | 3473 · 120 employers |
| Median days open | 128 d | 76 d (+52 d vs this employer) |
| Median salary (USD postings) | — | $230k |
Skills observed across this category: SoC architecture, Edge AI, SystemC, TLM, DSP, NPU
Who's hiring in this category
- Qualcomm · 78 open roles · median 89 d
- NVIDIA · 62 open roles · median 77 d
- Apple · 52 open roles · median 26 d
- AMD · 37 open roles · median 70 d
- Arm Holdings · 28 open roles · median 7 d
- Micron Technology · 21 open roles · median 111 d
How we counted: 490 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 4 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.