Systems Integration & Validation Engineer - Mountain View, CA, United States
$250,000 USD yearly
Originally posted 22 October 2026 by the employer.
Validate AI rack-scale systems spanning accelerator compute trays, host servers, liquid cooling, and L11 rack integration.
About the role
Own end-to-end validation of AI rack-scale systems from board and tray bring-up through full racks, multi-rack clusters, and L11 rack integration. The scope includes accelerator compute trays, host servers, scale-up switches, NICs, retimers, power shelves, busbars, liquid cooling, and rack management.
What you'll do
- Create system validation plans for AI rack-scale systems at the board, tray, rack, and multi-rack cluster levels through L11 rack integration. - Build validation environments including system diagnostics, stress and burn-in tests, workload-based tests, fleet health checks, and rack acceptance tests. - Develop test automation, telemetry collection, results databases, and dashboards for automated triage across racks and trays. - Lead system and rack bring-up from first power-on through validation, covering interoperability, power, thermal, performance characterization, margin testing, and reliability. - Drive validation across NPI phases (Proto, EVT, DVT, PVT, and production) and define entry and exit criteria. - Debug issues across silicon, board, firmware (BIOS/UEFI, BMC, device firmware), OS, drivers, networking, power, and thermal.
What you'll need
- 5+ years of experience in system validation, system integration, or bring-up for servers, accelerators, or rack-scale systems. - Strong coding skills in Python, C, and C++, alongside Linux systems experience. - Experience with BMC (OpenBMC), Redfish, and IPMI. - Experience validating hardware across NPI phases (Proto, EVT, DVT, PVT) and working with ODM and CM partners on L6, L10, and L11 test content. - Fluency with debug tools such as PCIe and Ethernet protocol analyzers, oscilloscopes, logic analyzers, and JTAG debuggers. - Expertise in one or more core domains: PCIe Gen5/6/7, CXL, 112G/224G SerDes, scale-up fabrics, RDMA/RoCE, liquid cooling, rack power delivery, RAS, or AI workloads.
This role has been open 0 days — well below the 34-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
562
|
Median days open
34 d
|
Median salary
$173k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | DensityAI | All employers we track in this specialty (562 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 562 |
| Open roles in the wider Silicon Validation & Test family | 4 | 2256 · 113 employers |
| Median days open | 21 d | 34 d (−13 d vs this employer) |
| Median salary (USD postings) | — | $173k |
Who's hiring in this category
- Teradyne · 81 open roles · median 26 d
- Infineon Technologies · 45 open roles · median 41 d
- Renesas Electronics · 45 open roles · median 27 d
- Micron Technology · 28 open roles · median 38 d
- Qualcomm · 28 open roles · median 34 d
- Texas Instruments · 25 open roles · median 29 d
How we counted: 562 open Silicon Test Engineering (DFT Test) roles from 78 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.