System Verification Co-Design Engineer - Speed and Rel - CA, Santa Clara, United States
$136,000 - $264,500 USD yearly
Originally posted 28 July 2026 by the employer.
About the role
As a System Verification Co-Design Engineer, you will work on system-level speed features, develop verification collaterals and automation infrastructure to characterize and validate them, and lead debug of complex silicon issues.
What you'll do
- Collaborate cross-functionally with system architects, hardware, firmware/software, process/reliability, and operations teams to co-design system-level speed features. - Understand system-level behavior and speed reliability margins, bounding box constraints, and identify solutions that optimize margins. - Translate hardware features and architectural requirements into verification techniques that achieve full coverage across testing flows. - Perform closed-loop validation by correlating silicon behavior against timing simulation and design expectations. - Define, prototype, and refine pre- and post-silicon bring-up flows to ensure product quality, performance, and schedule efficiency. - Design and implement automation tools for system speed modeling, applying AI and LLM-assisted workflows to compress characterization and debug cycles.
What you'll need
- MS in EE, CE, Systems Engineering, or equivalent experience. - 4+ years of experience in a related hardware engineering role. - Hands-on experience with silicon bring-up, frequency and power characterization, PPA analysis in pre- and post-silicon phases, tester-to-system correlation, and lab instrumentation (oscilloscopes, multimeters, DAQs). - Scripting proficiency in Python and/or Perl across Windows, Linux, and Android environments. - Familiarity with statistical methods and data analysis tools such as JMP. - Demonstrated use of AI or LLM-based tools (e.g., Claude, Copilot, ChatGPT) in an engineering workflow for scripting, log triage, and data analysis.
Skills: silicon bring-up, frequency characterization, power analysis, system-level issues, testability features
This role has been open 106 days — well above the 43-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
420
|
Median days open
43 d
|
Median salary
$168k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (420 roles · 62 employers) |
|---|---|---|
| Open roles in this specialty | 25 | 420 |
| Open roles in the wider Silicon Validation & Test family | 91 | 2244 · 112 employers |
| Median days open | 22 d | 43 d (−21 d vs this employer) |
| Median salary (USD postings) | — | $168k |
Skills observed across this category: silicon bring-up, frequency characterization, power analysis, system-level issues, testability features
Who's hiring in this category
- AMD · 57 open roles · median 47 d
- Micron Technology · 38 open roles · median 39 d
- Qualcomm · 38 open roles · median 27 d
- NVIDIA (this employer) · 26 open roles · median 24 d
- Microchip Technology · 22 open roles · median 72 d
- Graphcore · 20 open roles · median 125 d
How we counted: 420 open Post-Silicon Validation (Silicon Validation) roles from 62 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.