System Validation Engineer - Haifa District, Israel
Originally posted 17 August 2026 by the employer — open 28 days.
Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions with CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies.
About the role
This role involves hands-on post-silicon validation, focusing on PCIe link bring-up, physical-layer debug, and silicon validation of connectivity solutions that integrate CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies.
What you'll do
- Perform hands-on post-silicon validation.
- Debug PCIe link issues including link training, LTSSM, equalization, recovery, resets, and link stability.
- Analyze PCIe state-machine traces, protocol traces, registers, logs, eye diagrams, and lab measurements.
- Drive complex issues from initial failure through root-cause analysis and final resolution.
- Develop and execute PCIe validation plans, stress tests, corner-case scenarios, and interoperability tests.
- Develop automation to improve validation coverage, debug efficiency, and regression testing.
What you'll need
- BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
- 5+ years of engineering experience in silicon validation, post-silicon debug, or high-speed interface development.
- Strong hands-on knowledge of PCIe architecture and protocol.
- Experience working with PCIe analyzers, state traces, registers, logs, eye diagrams, and/or signal-integrity measurements.
- Experience working across hardware, firmware, and software boundaries.
- Scripting/programming skills, preferably Python.
- Linux knowledge and experience with Linux PCIe debug tools.
Nice to have
- Experience with PCIe Gen4/Gen5/Gen6/Gen7.
- Hands-on experience with PCIe PHY, SerDes, equalization, lane margining, or signal integrity.
- Experience with PCIe compliance and interoperability testing.
- Experience debugging intermittent, marginal, thermal-sensitive, or corner-case PCIe failures.
- Experience with PCIe switches, or networking/accelerator platforms.
- Practical experience using AI/ML tools for engineering debug and automation.
This role has been open 28 days — well below the 53-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Design Verification
|
Open roles in category
115
|
Median days open
53 d
|
Median salary
$162k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (115 roles · 24 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 115 |
| Open roles in the wider Silicon Validation & Test family | 17 | 1957 · 109 employers |
| Median days open | 28 d | 53 d (−25 d vs this employer) |
| Median salary (USD postings) | — | $162k |
Who's hiring in this category
- AMD · 19 open roles · median 33 d
- NVIDIA · 17 open roles · median 47 d
- Qualcomm · 15 open roles · median 34 d
- Graphcore · 9 open roles · median 89 d
- Altera · 6 open roles · median 19 d
- Amazon · 6 open roles · median 13 d
How we counted: 115 open Post-Silicon Validation (Design Verification) roles from 24 employers tracked in the SemiconductorJobs index, counted 14 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.