System Technology Research Engineer - (PhD Intern) - United States
$141,998 - $142,002 USD yearly
Originally posted 3 September 2026 by the employer. Relisted by the employer on 14 September 2026.
About the role
This internship focuses on developing System Technology Co-optimisation (STCO) methodology and evaluating 3D/2.5D dis-aggregation schemes for memory and logic stacking across different product architectures. You will contribute to Intel's semiconductor processing and packaging roadmap.
What you'll do
- Develop and enhance System Technology Co-optimisation (STCO) methodologies.
- Perform system-level evaluations of novel devices, interconnects, patterning, materials, systems, and integration schemes.
- Collaborate with diverse teams to advance innovation.
What you'll need
- Active Ph.D. candidacy in Electrical Engineering, Electronics Engineering, Computer Architecture and Design or similar.
- 1-2+ years research experience relevant to System architecture modelling, digital circuit analysis and design, VLSI physical layout, electronic design automation, or multi-physics modeling of electronic materials or systems.
- Familiarity with IC design and physical layout tools such as Cadence Virtuoso or Synopsis Fusion Compiler.
Nice to have
- System architecture design and modelling.
- IC design, simulation, physical layout, and tapeout experience.
- Familiarity with DRAM and SRAM circuit design and layout.
- Familiarity with integrated circuits manufacturing flow and requirements.
- Familiarity with different 2.5D and 3D packaging technologies.
- 3DIC design and simulation experience.
- Programming skills, preferably in Python.
Skills: STCO, 3D/2.5D dis-aggregation, hybrid bonding, memory and logic stacking, system architecture modelling, IC design
This role has been open 19 days — well below the 82-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Chiplet Interconnect
|
Open roles in category
40
|
Median days open
82 d
|
Median salary
$217k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Intel Corporation | All employers we track in this specialty (40 roles · 20 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 40 |
| Median days open | 89 d | 82 d (+7 d vs this employer) |
| Median salary (USD postings) | — | $217k |
Skills observed across this category: STCO, 3D/2.5D dis-aggregation, hybrid bonding, memory and logic stacking, system architecture modelling, IC design
Who's hiring in this category
- Marvell Technology · 5 open roles · median 21 d
- Qualcomm · 5 open roles · median 85 d
- Micron Technology · 4 open roles · median 132 d
- NVIDIA · 4 open roles · median 44 d
- AMD · 3 open roles · median 47 d
- Applied Materials · 2 open roles · median 73 d
How we counted: 40 open Chiplet/Advanced Packaging Design (Chiplet Interconnect) roles from 20 employers tracked in the SemiconductorJobs index, counted 23 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.