System & IO Architect - Signal Integrity
$177,000 - $387,000 USD yearly
Originally posted 20 April 2026 by the employer — open 143 days.
This role focuses on early-phase SI architecture exploration for high-speed memory and system interfaces.
About the role
This role involves independently modeling, simulating, and assessing high-speed interfaces, translating findings into architectural intent and requirements. It focuses on early-phase SI architecture exploration for high-speed memory and system interfaces.
What you'll do
- Define SI architectural strategies for high-speed memory and system interfaces
- Perform early feasibility and scaling analysis for future data rates
- Build hands-on channel models across package, board, and system
- Drive end-to-end SI co-design with IO, package, and system architects
- Translate SI insights into electrical requirements and architectural constraints
What you'll need
- Bachelor’s degree in Electrical Engineering or related field
- 10+ years of experience in signal integrity or high-speed interface design
- Strong hands-on SI modeling and simulation experience
- Deep understanding of transmission lines, jitter, loss, and crosstalk
Nice to have
- Master’s degree in a related technical field
- Experience with memory interfaces or high-speed IO standards
- Background in architecture or pre-silicon exploration roles
- Strong communication of complex SI trade-offs to leadership
- Experience using AI/LLM productivity tools
Skills: SI architectural strategies, high-speed memory, system interfaces, channel models, transmission lines, jitter, loss, crosstalk
This role has been open 138 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 8 | 217 |
| Median days open | 115 d | 91 d (+24 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SI architectural strategies, high-speed memory, system interfaces, channel models, transmission lines, jitter, loss, crosstalk
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.