System FPGA Engineer - Santa Clara, California, United States of America
$151,800 - $227,800 USD yearly
Originally posted 17 July 2026 by the employer.
Implement FPGA architectures for control-plane and telemetry systems using SystemVerilog and cocotb.
About the role
As a System FPGA Engineer, you will implement defined FPGA architectures for control-plane and telemetry systems on server reference platforms. You will contribute hands-on across RTL development, simulation, verification, testing, and lab bring-up.
What you'll do
- Implement synthesizable RTL designs based on defined system architectures using Verilog and/or SystemVerilog. - Develop and execute test benches and verification plans using Python-based scripts and cocotb. - Perform FPGA synthesis, place-and-route, and timing closure using vendor toolchains. - Test and debug FPGA designs in the lab using hardware bring-up tools, JTAG, logic analyzers, and oscilloscopes. - Collaborate with hardware, firmware, and software teams during system bring-up and integration phases. - Maintain and contribute to source-controlled design repositories using git and GitHub for CI/CD workflows and peer code reviews.
What you'll need
- Bachelor's degree in Engineering, Information Systems, Computer Science, or a related field with 4+ years of systems engineering or FPGA experience (or Master's degree with 3+ years, or PhD with 2+ years). - At least 5 years of experience in FPGA implementation and verification. - Proficiency in HDL development with Verilog and/or SystemVerilog, including simulation, test bench creation, synthesis, and debugging. - Experience with interfaces such as I2C, UART, AXI4, PCIe, DDR5, or similar protocols. - Proficiency in Python scripting and experience with cocotb for Python-based RTL verification. - Hands-on experience with FPGA development tools, hardware bring-up, JTAG, logic analyzers, and oscilloscopes.
Nice to have
- Master's degree in Computer Science/Engineering, Electrical Engineering, or a related field with 10 years of hands-on experience in FPGA implementation, verification, and system integration. - Advanced proficiency with high-speed interfaces including SerDes, PCIe 5/6, DDR5, or LPDDR5X. - Experience with embedded soft-core processor integration such as MicroBlaze, NIOS II, or RISC-V. - Familiarity with vendor-specific toolchains such as AMD/Xilinx Vivado/Vitis or Intel/Altera Quartus Prime. - Experience authoring timing constraints (XDC/SDC) and performing timing closure on complex multi-clock designs. - Knowledge of Clock Domain Crossing (CDC) techniques, formal CDC analysis methodologies, SystemVerilog Assertions (SVA), and functional coverage. - Background in server management standards such as IPMI, MCTP, PLDM, or OpenBMC ecosystems.
This role has been open 95 days — well above the 63-day median for FPGA Design roles.
FPGA Design · RTL Design
|
Open roles in category
102
|
Median days open
63 d
|
Median salary
$163k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (102 roles · 25 employers) |
|---|---|---|
| Open roles in this specialty | 8 | 102 |
| Median days open | 45 d | 63 d (−18 d vs this employer) |
| Median salary (USD postings) | — | $163k |
Who's hiring in this category
- Altera · 31 open roles · median 56 d
- AMD · 11 open roles · median 58 d
- Teradyne · 10 open roles · median 73 d
- Qualcomm (this employer) · 8 open roles · median 45 d
- Microchip Technology · 6 open roles · median 96 d
- Analog Devices · 4 open roles · median 96 d
How we counted: 102 open FPGA Design (RTL Design) roles from 25 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.