Synthesis-DFT Stitch CAD Engineer
$164,000 - $246,000 USD yearly
Originally posted 10 July 2026 by the employer. Relisted by the employer on 7 August 2026.
About the role
This role defines and develops implementation tools and methodologies for gate-level synthesis and DFT stitch solutions supporting Snapdragon chips. Work focuses on optimizing PPA and shortening design turnaround time across mobile, compute, AI, and IoT platforms.
What you'll do
- Develop Qualcomm DFT stitch flows and methods using Synopsys and Cadence EDA solutions. - Improve SoC synthesis and DFT stitch methodologies for complex multi-voltage crossings and timing constraints. - Enable new synthesis and DFT stitch checking features within commercial EDA tools and internal toolsets. - Support Snapdragon design teams on CAD solutions, investigate design issues, and resolve tickets. - Interface with EDA vendors and application engineers to resolve block convergence, cell legalization, congestion hotspots, and DFT stitch failures. - Set up and maintain regression test suites for complex synthesis and DFT stitch testcases.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field with 6+ years of ASIC design, verification, validation, integration, or related experience (or Master's with 5+ years, or PhD with 4+ years). - Experience in ASIC design implementation across synthesis, DFT, and place and route flows. - Experience with EDA tools from Synopsys and Cadence. - Hands-on CAD development skills focused on automation, PPA optimization, and flow enablement.
Nice to have
- Bachelor's, Master's, or PhD in Computer Engineering, Electrical Engineering, or a related field. - 5-10 years of experience in VLSI CAD, specifically synthesis, DFT, and P&R. - 5-10 years of experience with scripting tools and programming languages, with Python and TCL preferred.
Skills: DFT stitch flow, EDA tools, Synthesis, CAD solutions, Python, TCL
This role has been open 102 days — well above the 72-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
674
|
Median days open
72 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (674 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 36 | 674 |
| Open roles in the wider Physical Implementation family | 161 | 1441 · 110 employers |
| Median days open | 78 d | 72 d (+6 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: DFT stitch flow, EDA tools, Synthesis, CAD solutions, Python, TCL
Who's hiring in this category
- Cadence Design Systems · 154 open roles · median 152 d
- Synopsys · 61 open roles · median 39 d
- Micron Technology · 45 open roles · median 49 d
- Qualcomm (this employer) · 36 open roles · median 78 d
- GlobalFoundries · 34 open roles · median 37 d
- Keysight Technologies · 32 open roles · median 75 d
How we counted: 674 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.