Substrate IC Package Layout Design Engineer - San Jose, United States

Originally posted 27 August 2026 by the employer.

About the role

As a Substrate IC Package Layout Design Engineer, you will be responsible for the end-to-end design of complex IC substrate packages, supporting high-power consumption and high-speed signaling.

What you'll do

• Lead the design and development of complex IC substrate layouts for high-power AI processors and accelerators.
• Design large (>50mm) and complex multi-layer substrate packages with high pin counts and dense routing requirements.
• Develop high-speed signal routing solutions capable of supporting >50GHz signaling.
• Optimize CoWoS (Chip-on-Wafer-on-Substrate) interposer designs for thermal and electrical performance.
• Perform DRC (Design Rule Check) and LVS (Layout vs. Schematic) verification for all substrate designs.
• Develop and maintain design documentation and guidelines for future substrate designs.

What you'll need

• 10+ years of experience in IC substrate layout design for high-performance processors or accelerators.
• Extensive experience with large substrate packages (>50mm) and complex high-density layouts.
• Proven experience with high-power (700W+) package designs and robust power delivery networks.
• Expertise in high-speed signaling design (>50GHz) and mitigating signal integrity challenges.
• Strong experience with CoWoS (Chip-on-Wafer-on-Substrate) interposer design.
• Advanced proficiency in Allegro Package Designer (including constraint management, routing, and design verification).
• Deep understanding of SI/PI principles and how they apply to package-level design.

Skills: IC substrate layout, CoWoS integration, high-speed signal routing, SI/PI, Allegro Package Designer