Static Timing Analysis Engineer - Austin, United States
$160,650 - $298,350 USD yearly
Originally posted 22 October 2026 by the employer.
Work on timing constraints and timing closure signoff for low-power wireless SoCs featuring deeply gated asynchronous clock networks.
About the role
This position involves the development of timing constraints and timing closure signoff for low-power wireless SoCs and IP systems. The target devices include multi-core, multi-threaded processor subsystems with multi-level cache, multi-protocol wireless support, sensor hub, and AI/ML functionality across complex, deeply gated clock networks with asynchronous clock sources.
What you'll do
- Develop timing constraints at both the IP and SoC level in collaboration with design engineers. - Improve and evolve existing static timing analysis flows and methodologies. - Define required timing signoff criteria, including aging, on-chip variation, and signal integrity. - Analyze timing reports using scripting techniques to generate insights and drive rapid timing closure. - Collaborate with global and multi-functional design teams to resolve static timing issues and close timing for mixed-signal IP integration.
What you'll need
- Bachelor's or Master's degree in Electrical or Computer Engineering and 8+ years of experience. - In-depth knowledge of timing closure flows, methodologies, modes, and corners. - Experience developing timing constraints for functional and test modes, such as scan. - Hands-on experience with static timing tools, specifically Tempus or Primetime. - In-depth scripting experience using Perl, Python, Tcl, or shell. - Working knowledge of low-power design methodologies, including static/dynamic clock gating, power gating, and dynamic voltage and frequency scaling. - Knowledge of timing model generation for mixed-signal IP, as well as design flows covering Lint, CDC, Synthesis, Logic Equivalence, DFT, Place and Route, Verilog, and System Verilog.
Skills: STA, timing constraints, Primetime, Tempus, timing closure
This role has been open 0 days — well below the 62-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
664
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Silicon Labs | All employers we track in this specialty (664 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 664 |
| Open roles in the wider Physical Implementation family | 3 | 1489 · 110 employers |
| Median days open | 51 d | 62 d (−11 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: STA, timing constraints, Primetime, Tempus, timing closure
Who's hiring in this category
- Qualcomm · 119 open roles · median 45 d
- AMD · 61 open roles · median 27 d
- Intel Corporation · 40 open roles · median 15 d
- NVIDIA · 38 open roles · median 67 d
- Synopsys · 38 open roles · median 36 d
- Broadcom · 35 open roles · median 101 d
How we counted: 664 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.