Static Timing Analysis Design Engineer / Physical Design - Austin (Oakhill, Office), United States

Originally posted 14 October 2026 by the employer.

Drive end-to-end timing signoff for advanced semiconductor products at 5nm nodes.

About the role

This role involves owning end-to-end Timing Constraints and Static Timing Analysis across complex SoC designs, driving initial constraints development and timing correlation to final Timing Signoff for advanced technology nodes. This position focuses on closing timing for flagship SoCs at advanced nodes, impacting silicon success and product competitiveness.

What you'll do

• Own end-to-end Timing Constraints and Static Timing Analysis across complex designs.
• Drive Timing Constraints Creation and Validation.
• Collaborate with Frontend, IP, and DFT teams to validate constraints and resolve timing issues.
• Perform Timing Correlation and Timing Path Debug from synthesis through timing signoff.
• Provide timing feedback during all design stages and create Automated and Manual timing fixes for implementation.
• Provide feedback to improve scalability, productivity, and design quality through methodology enhancements.

What you'll need

• Bachelor’s or Master’s in Electrical / Electronics Engineering or related field.
• 3-6 years of experience in ASIC / SoC Timing Analysis.
• Strong knowledge of industry STA tools (Synopsys flows).
• Expertise in STA and signoff methodologies.
• Experience with Timing ECO Generation (automated and manual).
• Proficiency in Constraints Development and Validation.
• Experience with advanced node implementation (≤ 16nm / 5nm).
• Scripting skills in Python, TCL, and Perl.

Nice to have

• Experience in high-reliability SoCs.
• Exposure to AI-driven design methodologies and automation.
• Familiarity with using AI to generate scripts.

industry_context='', meta_title='Static Timing Analysis Design Engineer / Physical Design - NXP Semiconductors Austin', meta_description='NXP Semiconductors is seeking a Static Timing Analysis Design Engineer / Physical Design in Austin. Own end-to-end timing constraints and STA for advanced semiconductor products.', seo_keywords=['static timing analysis', 'physical design', 'timing signoff', 'constraints', 'eco', 'advanced node', 'asic', 'synopsys', 'python', 'tcl', 'perl'], screening_questions=['Do you have 3-6 years of experience in ASIC / SoC Timing Analysis?', 'Do you have strong knowledge of industry STA tools (Synopsys flows)?', 'Do you have experience with advanced node implementation (≤ 16nm / 5nm)?', 'Are you proficient in scripting with Python, TCL, and Perl?'], json_ld={}))偎

Skills: STA, timing signoff, constraints, ECO, advanced node, ASIC