$147,800 - $251,200 USD yearly
Digital design in NAND Flash memory covering microarchitecture, RTL design, logic synthesis, and timing analysis.
Originally posted 2 September 2026 by the employer.
About the role
This role is responsible for all aspects of digital design in NAND Flash memory, focusing on micro architecture, RTL design, verification, logic synthesis, and timing analysis to deliver a design meeting target power, performance, and area goals.
What you'll do
- Execute RTL design and verification in Verilog, including RTL linting, clock domain crossing (CDC) analysis, design integration, synthesis, DFT, timing analysis, and closure.
- Balance design trade-offs across modularity, scalability, power, area, and performance.
- Interface with internal and external teams and customers to define technical specifications and features.
- Participate in post-silicon evaluation and debug.
- Drive cross-functional support for productization while providing technical guidance and mentoring to junior engineers.
What you'll need
- Master of Science in Electrical Engineering or related field, plus 6-8 years of relevant experience.
- Experience with chip-level integration, chip lead responsibilities, and the full product life cycle (requirements, design, implementation, test) of logic design.
- Working knowledge of the entire logic design flow from RTL to GDSII, including RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion, place-and-route, clock tree synthesis, extraction, and physical verification.
- Working knowledge of NAND Flash memory cell device operations and algorithms for program/read/erase.
Nice to have
- Experience developing digital circuit designs for low-power operating conditions.
- Working knowledge of device physics, process, and NAND Flash memory design including Analog, Core, Datapath, and IO circuits.
- Proficiency with digital design tools such as Synopsys Design Compiler, Cadence Genus, Cadence RTL Compiler, Synopsys PrimeTime, Cadence Tempus, Synopsys ICC, Cadence Encounter, or Innovus.
- Familiarity with revision control tools and EDA standard formats used in cell/library development and modeling, such as Liberty and SDC (Synopsys Design Constraints).
- Programming experience in C, C++, Python, or Perl.
Skills: NAND Flash, RTL design, Verilog, logic synthesis, timing analysis
More semiconductor jobs: SanDisk jobs
This role has been open 6 days — well below the 72-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
302
|
Median days open
72 d
|
Category median salary (all employers)
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SanDisk | All employers we track in this specialty (302 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 15 | 302 |
| Median days open | 6 d | 72 d (−66 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: NAND Flash, RTL design, Verilog, logic synthesis, timing analysis
Who's hiring in this category
- Micron Technology · 154 open roles · median 82 d
- Synopsys · 30 open roles · median 77 d
- Qualcomm · 18 open roles · median 106 d
- Broadcom · 16 open roles · median 78 d
- SanDisk (this employer) · 15 open roles · median 7 d
- NVIDIA · 8 open roles · median 59 d
How we counted: 302 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 6 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.
