Staff Verification Engineer - Chandler, United States
Originally posted 1 October 2026 by the employer.
About the role
This role involves the verification and modeling of mixed-signal Automotive power management devices, including PMICs, switching regulators, and related analog IP.
What you'll do
- Design and architect mixed-signal verification environments, including Real Number Model (RNM) and AMS model integration for PMIC designs.
- Develop and implement comprehensive verification plans and strategies for automotive PMIC products, ensuring compliance with automotive safety standards (ISO 26262, AEC-Q200).
- Lead debugging activities for complex analog blocks including switched-mode regulators, Linear Dropout (LDO) regulators, and mixed-signal interfaces.
- Set up and optimize Gate-Level Simulation (GLS) flows, correlating with RTL simulation results.
- Conduct in-depth RTL and Gate-Level simulations, analyzing timing, power, and functional correctness across process, voltage, and temperature (PVT) corners.
- Drive continuous improvement of verification tools, methodologies, and infrastructure, evaluating emerging verification technologies.
What you'll need
- MS or PhD in Electrical Engineering, Computer Engineering, or related field.
- 12+ years of experience in mixed-signal or analog circuit verification.
- Deep understanding of mixed-signal verification environment architecture and implementation.
- Hands-on experience with Real Number Model (RNM) and AMS model integration.
- Proficiency in RTL and behavioral simulation tools (e.g., Spectre, Xcelium).
- Strong understanding of Gate-Level Simulation (GLS) flows and ability to set up and debug GLS simulations.
- Proven expertise debugging both analog blocks (switched-mode regulators, LDO, bandgap, reference circuits) and digital RTL.
- Experience with automotive PMIC or power management IC design and verification.
- Proficiency in Verilog, SystemVerilog, and/or SPICE-based languages.
- Solid understanding of verification methodologies: UVM, assertions, coverage-driven verification.
- Experience interfacing with multiple verification domains: functional, post-silicon, ATE test correlation.
- Leadership and mentoring experience.
Skills: mixed-signal verification, PMIC, AMS model, UVM, SystemVerilog, ISO 26262
This role has been open 12 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1191
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (1191 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 29 | 1191 |
| Open roles in the wider Digital Design & Verification family | 83 | 3166 · 114 employers |
| Median days open | 15 d | 64 d (−49 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: mixed-signal verification, PMIC, AMS model, UVM, SystemVerilog, ISO 26262
Who's hiring in this category
- Qualcomm · 104 open roles · median 44 d
- AMD · 102 open roles · median 53 d
- NVIDIA · 77 open roles · median 66 d
- Synopsys · 61 open roles · median 29 d
- SiFive · 54 open roles · median 70 d
- Cadence Design Systems · 51 open roles · median 112 d
How we counted: 1191 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 13 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.