Staff Verification Applications Engineer
Originally posted 20 September 2026 by the employer — open 1 day.
About the role
This Staff Verification Applications Engineer role drives customer deployments of VCS and Verdi simulation and debug technology, integrating tools into existing flows.
What you'll do
- Drive customer deployments of VCS and Verdi simulation and debug technology.
- Diagnose and resolve complex technical issues across UVM testbenches, SVA assertions, Low Power UPF flows, and Gate Level Timing simulations.
- Collaborate with global R&D and product teams to gather customer requirements and influence the product roadmap.
- Lead competitive engagements by running benchmarks and demonstrating VCS/Verdi advantages.
- Develop and optimize automation scripts in Perl, Tcl, Python, Shell, and Make.
- Interface directly with customers, product validation teams, and R&D to propose solutions.
What you'll need
- Bachelor's or Master's degree in Electronics Engineering or related field with 5-12 years of hands-on experience in verification or applications engineering.
- Strong working knowledge of VCS simulation technology and Verdi debug platform, or equivalent simulation and waveform debug tools.
- Deep expertise in SystemVerilog, UVM, SVA, and verification methodologies applied to real RTL designs.
- Proven experience with Low Power UPF flows and Gate Level Timing simulations.
- Advanced scripting ability in Perl, Tcl, Python, Shell, and Make for automation and flow development.
- Solid understanding of digital design fundamentals, Verilog, VHDL, and UNIX/Linux environments.
Nice to have
- Exposure to DPI, C/C++, SystemC, Functional Safety, or GenAI technologies.
Skills: VCS simulation, Verdi debug, UVM testbenches, SystemVerilog, SVA assertions
This role has been open 0 days — well below the 60-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1136
|
Median days open
60 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (1136 roles · 94 employers) |
|---|---|---|
| Open roles in this specialty | 62 | 1136 |
| Open roles in the wider Digital Design & Verification family | 131 | 3020 · 114 employers |
| Median days open | 16 d | 60 d (−44 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: VCS simulation, Verdi debug, UVM testbenches, SystemVerilog, SVA assertions
Who's hiring in this category
- Qualcomm · 103 open roles · median 55 d
- AMD · 101 open roles · median 33 d
- NVIDIA · 89 open roles · median 67 d
- Synopsys (this employer) · 58 open roles · median 22 d
- Micron Technology · 56 open roles · median 100 d
- SiFive · 52 open roles · median 48 d
How we counted: 1136 open Design Verification (Design Verification) roles from 94 employers tracked in the SemiconductorJobs index, counted 21 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.