Staff Technical Program Manager, ASIC - Austin, Texas, United States

Originally posted 10 September 2026 by the employer.

Drive the Electronic IC (EIC) program end-to-end, from architecture convergence to post-silicon bring-up and system integration.

About the role

This role involves driving the end-to-end program for the Electronic IC (EIC), a high-speed mixed-signal ASIC central to Neurophos' optical compute engine. The EIC drives, reads out, and controls photonic hardware and connects it to the rest of the system.

What you'll do

• Drive the end-to-end EIC program, including integrated schedule, milestones, dependency map, staffing outlook, and risk register.
• Champion the AI-first development flow, deploying AI/LLM tooling across spec and requirements management, schedule, risk registers, and status reporting.
• Partner with the architecture team to converge the EIC specification, driving design reviews, decision logs, and change control.
• Drive execution across RTL, DV, analog/mixed-signal, DFT, and physical design teams, coordinating external partners like IP vendors and foundry.
• Build and drive the tapeout readiness checklist, including verification closure, signoff, DRC/LVS, and mask release.
• Manage the foundry engagement day-to-day, covering shuttle and full-mask schedules, PDK/deck updates, wafer starts, and delivery tracking.
• Drive post-tapeout execution, including bring-up plan, lab readiness, package/assembly coordination, ATE/bench test planning, silicon debug, and errata tracking.
• Track cross-domain dependencies between the EIC and photonic IC, package/substrate, board, firmware, and software teams.

What you'll need

• BS in Electrical/Computer Engineering or equivalent (MS preferred).
• 10+ years in ASIC/SoC development as a TPM/EPM or equivalent lead role on complex silicon programs.
• 2+ complete silicon programs taken from architecture/specification through tapeout, with at least one carried through post-silicon bring-up to production.
• Working fluency across the full silicon lifecycle: architecture, front-end design, verification, FPGA/emulation, physical design, DFT, signoff, package/substrate design, foundry manufacturing, bring-up, ATE, and reliability/qualification.
• Direct experience managing foundry, IP vendor, OSAT, and design-services relationships, including tapeout logistics and mask releases.
• Technical depth to communicate credibly with engineers across the design stack, pressure-test schedules, and understand technical risks.
• Demonstrated cross-functional leadership, aligning multiple engineering teams and external partners without direct authority.
• Hands-on command of program tooling (Jira or equivalent, dependency/schedule tracking, dashboards and checklists).
• Fluent, daily use of AI tools in program work and an automate-first instinct with judgment about AI output verification.

Nice to have

• Mixed-signal or high-speed analog program experience (SerDes, data converters, drivers/TIAs) or exposure to optical transceivers / silicon photonics.
• Advanced packaging experience: 2.5D/3D integration, interposers, CoWoS, hybrid bonding.
• First-silicon or startup experience, familiar with building a program process from scratch.
• Prior hands-on background in design, DV, or physical design before moving into program management.
• Familiarity with formal gate-review frameworks (PDR/CDR) and requirements management.
• TPM experience on ML accelerator or data-center hardware programs (GPU, TPU, custom accelerators, networking).
• Hands-on experience deploying AI-assisted EDA, verification, or agentic engineering workflows on a real silicon program.

Skills: ASIC development, silicon lifecycle, tapeout, post-silicon bring-up, foundry management