Staff Systems Engineer, Calibration, Bring-Up & Verification - Austin, Texas, United States
Originally posted 18 September 2026 by the employer.
About the role
This role involves owning calibration architecture, system integration, and verification for an optical vector-matrix multiplication (OVMM) engine. The focus is on devising calibration algorithms for optical phase, amplitude, and timing, defining bring-up and verification strategies, and laboratory characterization of hardware.
What you'll do
- Define the calibration architecture for the OVMM system and scope algorithms for optical phase, amplitude, and timing.
- Design, implement, and optimize calibration algorithms using control theory and optimization techniques.
- Design and implement signal processing techniques within calibration loops to enhance measurement SNR.
- Develop techniques and algorithms to compress calibration data and minimize storage requirements.
- Specify calibration controller behavior, hardware structures, and define calibration software and firmware interfaces.
- Define system integration strategy, plan integration sequence, and lead laboratory bring-up and debug.
- Develop verification plans, execute performance characterization, and correlate measured results with modeled predictions.
What you'll need
- MS or PhD in Electrical Engineering, Applied Physics, or a closely related field, with emphasis on control systems, signal processing, or mixed-signal systems.
- 5+ years of professional experience in calibration algorithm development, system bring-up, or verification of complex electro-optic or mixed-signal systems.
- Strong foundation in feedback control (stability analysis, sampled-data systems) and optimization methods (convex optimization, gradient descent, search algorithms).
- Deep understanding of analog and mixed-signal impairments including noise, component mismatches, nonlinearities, and bandwidth limitations.
- Understanding of digital hardware design principles including logic synthesis, area and power estimation, state machine design, and fixed-point arithmetic.
- Hands-on experience bringing up and debugging complex hardware using oscilloscopes, spectrum/network analyzers, and optical test equipment.
- Proficiency developing calibration and test software (Python and/or MATLAB), including control loops, data acquisition, and automated characterization scripts.
Nice to have
- Practical experience with digital signal processing techniques including spectral analysis, correlation, and and adaptive filtering.
- Familiarity with Cadence Virtuoso and Spectre for validating calibration-relevant behavioral models.
- Exposure to Bayesian optimization, machine learning for system calibration, or statistical design of experiments.
- Experience with optical transceiver calibration, phased-array beamforming, or ADC/DAC calibration.
This role has been open 25 days — well below the 60-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Design Verification
|
Open roles in category
113
|
Median days open
60 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Neurophos | All employers we track in this specialty (113 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 113 |
| Open roles in the wider Silicon Validation & Test family | 1 | 2199 · 111 employers |
| Median days open | 25 d | 60 d (−35 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 18 open roles · median 43 d
- AMD · 15 open roles · median 60 d
- NVIDIA · 14 open roles · median 67 d
- Graphcore · 10 open roles · median 118 d
- Amazon · 6 open roles · median 37 d
- Synopsys · 6 open roles · median 6 d
How we counted: 113 open Post-Silicon Validation (Design Verification) roles from 29 employers tracked in the SemiconductorJobs index, counted 13 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.