Staff STA Engineer - Austin, Texas, United States
$198,100 - $268,000 USD yearly
Originally posted 27 July 2026 by the employer.
About the role
This role involves owning full chip and block level timing closure for complex multi-instantiated silicon compute sub-system solutions addressing markets such as premium mobile, infrastructure, and automotive. The work will involve innovative nodes such as 3nm and advanced SoC 2.5D and 3D technology.
What you'll do
- Own full chip and block level timing closure throughout the entire project cycle.
- Handle timing constraints for functional and test mode at different logical hierarchical levels.
- Work closely with various multi-functional teams on resolving complex timing issues for major building blocks of sophisticated SoCs.
- Generate ECOs at both block and top level, coordinating with the team for timing/functional ECO implementation.
What you'll need
- 6+ years of work experience in Timing convergence.
- Experience in industry standard STA tools and methodologies.
- Knowledge of timing corners/modes including DFT, process variations, and signal integrity issues.
- Work experience on timing closure for multi power domain designs.
- Experience in collaborating across silicon engineering groups and with EDA vendors.
- Experience with constraints development and timing closure on 5nm or 3nm technologies.
- Strong automation skills in Perl/Tcl/Python.
Nice to have
- Masters or equivalent experience in Electrical Engineering.
- Coding skills in Perl/Python or TCL or an equivalent language.
- Familiarity with synthesis, logic equivalence, DFT, CLP, and backend related methodology and tools.
Skills: Timing convergence, STA tools, timing closure, multi power domain, ECO
This role has been open 82 days — well above the 60-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
659
|
Median days open
60 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Arm Holdings | All employers we track in this specialty (659 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 659 |
| Open roles in the wider Physical Implementation family | 12 | 1441 · 110 employers |
| Median days open | 102 d | 60 d (+42 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: Timing convergence, STA tools, timing closure, multi power domain, ECO
Who's hiring in this category
- Qualcomm · 119 open roles · median 45 d
- AMD · 63 open roles · median 24 d
- NVIDIA · 37 open roles · median 72 d
- Synopsys · 37 open roles · median 32 d
- Intel Corporation · 36 open roles · median 11 d
- Broadcom · 30 open roles · median 97 d
How we counted: 659 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.