Staff - SoC RTL Design Engineer (UCIE) - Bengaluru, India

About the role

This role involves developing high-performance, scalable, and power-efficient digital designs for SoCs and Chiplets targeting AI, HPC, and Networking applications. This position requires deep expertise in RTL design, micro-architecture, and integration of high-speed interfaces for first-time silicon success.

What you'll do

• Specify and own the reset sequencing architecture, secure boot, and fuse micro-architecture and design.
• Coordinate with subsystem leads on reference clock distribution and clock-domain crossing points at subsystem interfaces.
• Collaborate with the firmware team to define the hardware/software interface: interrupt controller, timer, UART/JTAG debug port, DMA, or mailbox channels.
• Own the clock-gating implementation strategy, ICG cell selection, and sign-off methodology for dynamic power reduction.
• Define the chip-level power-domain plan, including level-shifters, isolation cells, and mapping power states to PCIe and UCIe link power management protocols.
• Own the on-chip power management logic: power-state machine, supply sequencing, voltage regulator integration, and the firmware interface for runtime power control.
• Drive power intent (UPF/CPF) authoring and sign-off, coordinating with the physical design team on power-domain floorplan, always-on routing, and isolation verification.
• Own the embedded management processor subsystem: processor integration, on-chip SRAM and ROM sizing, boot sequence, fuse and OTP interface, and firmware execution environment.
• Define the management register map for firmware configuration of operating modes, telemetry, power states, and DFT operations.
• Specify thermal monitoring integration: on-die temperature sensor placement, readout path to the management processor, and thermal throttling hooks.

What you'll need

• 8+ years of digital IC design, with at least 3 years owning chip infrastructure (clocking, power management, reset, or DFT) at block-lead or subsystem-owner level.
• Familiarity with embedded microcontroller integration: memory maps, boot ROM, interrupt controllers, and firmware bring-up at the hardware level.
• Experience with reset-domain architecture and reset synchronizer design in multi-power-domain chips.
• Strong SystemVerilog skills for infrastructure RTL: clock-gating cells, power FSMs, scan-enable muxing, and BIST controllers.
• BS/MS in Electrical Engineering, Computer Engineering, or equivalent.