Staff SoC Layout/EDA Designer - Ft. Lauderdale, FL, United States
Originally posted 4 August 2026 by the employer.
About the role
As Staff SoC Layout/EDA Designer, you will deliver System-on-Chip (SoC) products from concept to high volume production. This role focuses on analog/RF/mixed-signal layout in deep sub-micron CMOS nodes (40nm and lower).
What you'll do
- Create and optimize layouts of complex blocks and chip-level SoC macros with analog/RF/mixed-signal and digital engineers.
- Produce high-quality analog/RF/mixed-signal macros using industry best practices for layout and physical verification.
- Own block-level layout designs and top-level floor planning, including full hierarchical verification and debug.
- Lead, document, and communicate layout design flows and reviews, including the tape-out process and project database management/archive.
- Manage and support layout contractors and mentor junior layout designers.
- Collaborate with global team engineers and designers to ensure designs are specification compliant and on time.
What you'll need
- Minimum of Associate’s degree in Electronic Engineering or related field.
- 5+ years relevant industry work experience.
- Strong working skills with Cadence Virtuoso and PDK layout design tools (OA, CDL, GDS).
- Strong working skills with physical verification tools (Pegasus/Calibre) and flows (DRC, LVS, ERC, PERC, LVL).
- Detailed experience with analog/RF/mixed-signal layout in deep sub-micron, CMOS nodes (40nm and lower).
- Understanding of LDE, ANT, ESD/LUP, NTN/TW/SOI isolation, matching, PnR parasitics, and EMIR concepts.
- Knowledge of digital physical design flows and techniques (VHDL, Verilog, LEF, DEF).
- Knowledge of scripting with Linux shell, Makefile, Modules, SKILL, TCL, Python and/or AI-LLM clients.
Skills: analog/RF/mixed-signal layout, Cadence Virtuoso, PDK, physical verification, DRC/LVS
This role has been open 63 days — well below the 82-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
696
|
Median days open
82 d
|
Median salary
$190k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | QORVO | All employers we track in this specialty (696 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 696 |
| Open roles in the wider Physical Implementation family | 7 | 1455 · 108 employers |
| Median days open | 37 d | 82 d (−45 d vs this employer) |
| Median salary (USD postings) | — | $190k |
Skills observed across this category: analog/RF/mixed-signal layout, Cadence Virtuoso, PDK, physical verification, DRC/LVS
Who's hiring in this category
- Cadence Design Systems · 166 open roles · median 161 d
- Synopsys · 54 open roles · median 36 d
- Micron Technology · 40 open roles · median 115 d
- NVIDIA · 40 open roles · median 72 d
- Qualcomm · 37 open roles · median 75 d
- GlobalFoundries · 28 open roles · median 52 d
How we counted: 696 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 7 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.