Staff Silicon Design Engineer - MA, Boxborough, United States
Originally posted 1 October 2026 by the employer.
AMD focuses on developing unique solutions through Strategic Silicon Solutions (S3).
About the role
This Staff Silicon Design Engineer will act as a Senior Member of the Technical Staff for the pre-silicon IP design team, working with architecture, IP design verification, SOC design/verification, DFT, physical design, and product engineers to achieve first pass silicon success. This role involves designing IP subsystems, integrating AMD and 3rd party IP, and contributing to power-gated digital designs.
What you'll do
- Provide technical guidance to the design team.
- Plan team deliverables throughout the program.
- Design IP subsystems with integration of AMD and other 3rd party IP (ARM, DSPs, NOCs).
- Contribute to the specification and quality checks (lint, CDC, and power rule checks) of power-gated digital designs.
- Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC.
- Partner with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up.
What you'll need
- Significant full-time experience in IP hardware design.
- Experience in subsystem development with embedded processors and data fabric architectures.
- Proficiency in Verilog/SystemVerilog RTL logic design of high-speed, multi-clock digital designs.
- Detailed understanding of ASIC design flows.
- Experience with power saving techniques, including clock gating and UPF-based power gating.
- Experience with Verilog simulation and lint tools.
- Experience with CDC/RDC concepts and tools.
Nice to have
- Prior technical leadership experience, subject matter expert.
- Prior team leadership experience (small/mid-sized team).
- Experience with 3rd party IP integration.
Skills: pre-silicon IP design, RTL logic design, ASIC design flows, Verilog/SystemVerilog, power-gated digital designs
This role has been open 14 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1021
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1021 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 72 | 1021 |
| Open roles in the wider Digital Design & Verification family | 254 | 3204 · 115 employers |
| Median days open | 36 d | 62 d (−26 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: pre-silicon IP design, RTL logic design, ASIC design flows, Verilog/SystemVerilog, power-gated digital designs
Who's hiring in this category
- Qualcomm · 140 open roles · median 62 d
- Synopsys · 85 open roles · median 30 d
- AMD (this employer) · 71 open roles · median 36 d
- Analog Devices · 48 open roles · median 50 d
- NVIDIA · 46 open roles · median 64 d
- NXP Semiconductors · 41 open roles · median 85 d
How we counted: 1021 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.
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